Hfdth

Revised March 2000

DM74LS154
4-Line to 16-Line Decoder/Demultiplexer
General Description

Features

Each of these 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen mutually exclusive outputs when both the strobe inputs, G1 and G2, are LOW. The demultiplexing function is performed by using the 4 input lines to address the output line, passing data from one of the strobe inputs with the other strobe input LOW. When either strobe input is HIGH, all outputs are HIGH. These demultiplexers are ideally suited for implementing high-performance memory decoders. All inputs are buffered and input clamping diodes are provided to minimize transmission-line effects and thereby simplify system design.

s Decodes 4 binary-coded inputs into one of 16 mutually exclusive outputs s Performs the demultiplexing function by distributing data from one input line to any one of 16 outputs s Input clamping diodes simplify system design s High fan-out, low-impedance, totem-pole outputs s Typical propagation delay
3 levels of logic

23 ns

Strobe

19 ns

s Typical power dissipation 45 mW

Ordering Code:
Order Number

Package Number

Package Description

DM74LS154WM

M24B

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

DM74LS154N

N24A

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

© 2000 Fairchild Semiconductor Corporation

Logic Diagram

DS006394

www.fairchildsemi.com

DM74LS154 4-Line to 16-Line Decoder/Demultiplexer

August 1986

DM74LS154

Function Table
Inputs

Outputs

G1

G2

D

C

B

A

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

L

L

L

L

L

L

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

L

L

L

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

L

L

H

L

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

L

L

H

H