The Microarchitecture Level
IJVM Mic-1, instructions set architecture and control flow.
Speeding up the Mic-1 architecture (Mic-1 to Mic-4):
Multiple internal busses, instruction fetch unit (IFU), instruction prefetching, pipelining, etc.
Other Means to Improve Performance:
Cache, Branch Predication (Static and Dynamic), Out-of-order Execution, Register Renaming,
Speculative Execution, etc.
Application of improvements in Pentium class architectures
The Instruction Set Architecture Level
Programmer’s and User’s Manual for a Processor
Architecture, Data Types, Addressing and Memory Maps
0, 1, 2, 3, 4 – Address Instructions
Opcode composition, Opcode Design (Expanding Opcodes)
Immediate, direct, register, register indirect, indexed, based-indexed, stack, PC-Relative
Data Movement, Dyadic, Monadic, Comparisons and Conditional Branches, Procedure Calls,
Loop Control, Input and Output
Procedures, Coroutines, Traps, and Interrupts
Predication, Speculative Execution, Speculative Load etc.
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Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.
Exam Expected Format:
7-8 Questions Likely
Short answer question with multiple parts 2/4 points each, total 10/20 points.
Simple 5 point questions, or multiple part 5 point each question.
Basic 10 point questions, multiple parts can be expected.
Back of the envelope computation question(s).
All Chap. 4-5 topics … and anything recovered or extended.
IJVM MIC-1 architecture
IJVM new instruction sequence
IJVM Stack based code execution
IJVM instruction execution register content timing
ISAs for different microarchitectures
Addressing modes and Opcode Construction