Evolution of Industrial Relations in India
An analogue electronic circuits diagnosis with the use of evolutionary algorithms
Piotr Jantos Damian Grzechca Jerzy Rutkowski
Division of Circuits and Signals Theory Division of Circuits and Signals Theory Division of Circuits and Signals Theory Institute of Electronics Institute of Electronics Institute of Electronics Silesian University of Technology Silesian University of Technology Silesian University of Technology Gliwice, 44-100, Poland Gliwice, 44-100, Poland Gliwice, 44-100, Poland Email: jerzy.rutkowski@polsl.pl Email: damian.grzechca@polsl.pl Email: piotr.jantos@polsl.pl
Abstract— There is a method of global parametric faults location in analogue integrated circuits presented in this paper. Circuit Under Test is diagnosed in the time domain. The method is based on a utilisation of the tested device response and its derivative base features, i.e. following maxima and minima. The set consisted of base features is transformed into an advanced feature. Base features and the advanced feature are used in the process of faults location. There is a method allowing for testing time optimisation presented in this paper. The fault dictionary is constructed with the use of two evolutionary algorithms, i.e. gene expression programming and differential evolution. The presented diagnosis method has been verified with an exemplary circuit — a CMOS operational amplifier.
I. I NTRODUCTION Analogue integrated circuits (AIC) are playing a very important part in nowadays electronics. This trend is supported by the AIC manufacturers providing more advanced devices each year. Producing integrated circuits is the more expensive the more the circuit is complex. Thus, the manufacturers are putting their efforts into maximising production yield. One of the most important issues in a thorough developing of the AIC is creating diagnosis methods allowing for the prototype validation [1]. This problem is essential as the prototype phase of AIC life is the very moment any
Piotr Jantos Damian Grzechca Jerzy Rutkowski
Division of Circuits and Signals Theory Division of Circuits and Signals Theory Division of Circuits and Signals Theory Institute of Electronics Institute of Electronics Institute of Electronics Silesian University of Technology Silesian University of Technology Silesian University of Technology Gliwice, 44-100, Poland Gliwice, 44-100, Poland Gliwice, 44-100, Poland Email: jerzy.rutkowski@polsl.pl Email: damian.grzechca@polsl.pl Email: piotr.jantos@polsl.pl
Abstract— There is a method of global parametric faults location in analogue integrated circuits presented in this paper. Circuit Under Test is diagnosed in the time domain. The method is based on a utilisation of the tested device response and its derivative base features, i.e. following maxima and minima. The set consisted of base features is transformed into an advanced feature. Base features and the advanced feature are used in the process of faults location. There is a method allowing for testing time optimisation presented in this paper. The fault dictionary is constructed with the use of two evolutionary algorithms, i.e. gene expression programming and differential evolution. The presented diagnosis method has been verified with an exemplary circuit — a CMOS operational amplifier.
I. I NTRODUCTION Analogue integrated circuits (AIC) are playing a very important part in nowadays electronics. This trend is supported by the AIC manufacturers providing more advanced devices each year. Producing integrated circuits is the more expensive the more the circuit is complex. Thus, the manufacturers are putting their efforts into maximising production yield. One of the most important issues in a thorough developing of the AIC is creating diagnosis methods allowing for the prototype validation [1]. This problem is essential as the prototype phase of AIC life is the very moment any