# Cmos Inverter

Professor Sunil Bhave p CU School of Electrical and Computer Engineering February 8, 2010

Inverters I t

DC Analysis

Operating regions and voltage transfer curve Logic levels and noise margins

Transient Analysis - delay Power P

Objectives Obj ti

We have studied how a transistor can be viewed as a switch (switchview) We have derived the I-V model for a transistor Now with this simple model, we analyze the “electrical” properties of a CMOS inverter Noise Margin Delay Power Two outcomes: Analysis ability Understand concepts (intuition)

Reliability― Noise in Digital Integrated Circuits

v(t) i(t) ()

V DD

Inductive coupling

Capacitive coupling

Power and ground noise

DC Operation Voltage Transfer Characteristic

V(out)

Mapping between analog and digital signals

V out Slope = -1

V

OH

f V(y)=V(x)

VOH = f(VOL) VOL = f(VOH) VM = f(VM)

“ 1”

V OH V IH Undefined Region V

V

OH

VM Switching Threshold V OL V OL V OH V(in)

IL

Slope = -1 V OL V IL V IH V in

“ 0”

V

OL

Nominal Voltage Levels

Definitions D fi iti

VM VIL VOL VIH VOH

Definitions D fi iti

VM – Vout=Vin VIL – Slope = -1 VOL – Vout @ VIH VIH – Slope = -1 VOH – Vout @ VIL

Regenerative Property

out v3 v1 fin v(v) f (v)

Regenerative Property

v0 v1 v2 v3 v4 v5 v6

out v3 v1 v3 f (v)

V (Volt)

3

fin v(v)

A chain of inverters

5 v0

1

v1

v2 6 8 10

v2

0 Regenerative

v

in

v0

2 Non-Regenerative

v

in

Simulated response

21

0

2

4 t (nsec)

Noise M N i Margins i

How much noise can a gate input see before it does not recognize the input?

Noise B d t N i Budget

Allocates gross noise margin to expected sources of noise Sources: supply noise, cross t lk S l i talk, interference, offset Differentiate between fixed and proportional Diff ti t b t fi d d ti l noise sources

Key Reliability Properties

Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage)

Fan-in d F F i and Fan-out t

Noise immunity is the more important metric – the capability to suppress noise sources Key K metrics: Noise t ti N i transfer f f functions, Output impedance of the ti O t ti d f th driver and input impedance of the receiver; N

M

Fan-out N

Fan-in Fan in M

The Ideal Gate

V out

An Old-time Inverter

5.0 4.0 NM L

g=∞

Ri = ∞ Ro = 0 Fanout = ∞ NMH = NML = VDD/2

3.0

(V) 2.0 out V

VM NM H

1.0

V in

0.0

1.0

2.0

3.0 V in (V)

4.0

5.0

CMOS Inverter I t

DC Analysis:

Operating regions and voltage transfer curve (VTC) Logic Levels and Noise Margins VIH, VOH, VIL, VOL

DC R Response

DC Response: Vout vs Vin vs. for a gate Ex: CMOS Inverter

First order analysis: switch model When Vin = 0 -> Vout = VDD When Vin = VDD -> Vout = 0 Real analysis: transistor equations In between, Vout depends on transistor size and current By KCL, must settle such that Idsn = |Idsp| We l W solve equations ti

Transient Analysis

Delay (tHL and tLH)

Power Analysis and PDP (Power Delay Product)

Power Dissipation

CMOS Inverter Properties I t P ti

High and low levels = VDD GND VDD, Voltage swing = supply voltage -> high noise margins Logic levels *not* dependent on device sizes ratio-less ratio less In steady state, there is a path from either VDD or GND to the output Low output impedance Less sensitivity to noise Extremely high input resistance Steady state power is very low Fanout = ∞ (if you don’t care about speed!) No direct path between supply rails => no static power

Transistor Operation T i t O ti

Current depends on region of transistor behavior For what Vin and Vout are nMOS and pMOS in Cutoff? C ff? Linear? Saturation? S t ti ?

nMOS Operation MOS O ti

Cutoff Vgsn < Linear Vgsn > Vdsn < Saturated Vgsn > Vdsn >

nMOS Operation MOS O ti

Cutoff Vgsn < Vtn Linear Vgsn > Vtn Vdsn < Vgsn - Vtn...

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