Topics: MOSFET, CMOS, Logic gate Pages: 10 (1671 words) Published: July 23, 2013
CMOS INVERTER: Preliminary Questions and Design

Functional group F94

Basic CMOS Inverter Circuit and Operation of CMOS inverter

Kerk Yi Wern

Basic CMOS inverter Circuit

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Act like a switching circuit Input: High Input: Low NMOS ON , PMOS OFF PMOS ON, NMOS OFF

Operation of CMOS inverter

Rise/fall time, VTC, Noise margin effects and Threshold Voltage Vm.

Nabilah SK Aziz

→ The propagation delay of the CMOS inverter is determined by the time it takes to charge and discharge the capacitances present in the logic circuit → The two parameters are the high-to-low propagation time,tPHL and the low-to-high propagation time, tPLH. → tPLH is the time measured from the voltage on the falling input waveform to the same voltage on the rising output voltage. → For the low-to-high transition, the n-channel device is cutoff and the p-channel MOSFET is initially saturated and supplying - IDp(sat) to charge up the gate and parasitic capacitances → tPHL is the time measured from the voltage on the rising input waveform to the same voltage on thefalling input waveform. → VIN switches instantly from low to high. Driver transistor (n-channel) immediately switches from cutoff to saturation; the p-channel pull-up switches from triode to cutoff. → TP (propagation delay) = ( tPLH+ tPHL)/2

Output Rise Time (tPHL) and Output Fall Time (tPLH)


Noise margin is a measure of the circuit's immunity to noise. The high-level and low-level noise margins are represented by VNH and VNL respectively the ability of a logic circuit to tolerate noise without causing any unwanted changes in the output. Also, the quantative measure of noise immunity is known as noise margin.. Digital circuit working with logical Low-level and High-level. There is a noise margin build into the definition. If there is noise(on ground or supply voltage, or crosstalk to inputs) above the tolerable noise margin, you get malfunction or faulty function. Logic Noise Margin is the difference between what the driver IC outputs as a valid logic voltage and what the receiver IC expects to see as a valid logic voltage. There are two different types of noise margin, one for a logic high value [1] and one for a logic low value [0]. Noise Margin Output high = VOH [driving device] - VIH [receiving device] Noise Margin Output low = VIL [receiving device] - VOL [driving device]


The switching threshold, Vm, is defined as the point on the VTC where Vin = Vout=Vm. Vm value can be obtained graphically from the intersection of the VTC with the line Vin=Vout when Vin=Vout, both NMOS and PMOS transistor operate in the saturation region. Both transistor are also said ON at the same time and hence a direct conducting path will be established between VDD and GND. By equating these two transistor and solving the resulting equation, we can get the switching threshold voltage value


switching threshold (VM)

Switching threshold can be set by the ratio of relative driving strengths of the PMOS and NMOS transistors.

To move Vm upwards, a larger value of ratio is required, which means making the PMOS wider.

Increasing the strength of the NMOS, on the other hand, moves the switching threshold closer to GND.

Why is switching threshold important??? • The effect of changing the Wp/Wn ratio is to shift the transient region of the VTC. Increasing the width of the PMOS or the NMOS moves VM towards VDD or GND respectively.

Static Power, Dynamic Power,Current Flow in VTC Curve and working with inverters with limitations

Nor Zakiah Zahari

Static and Dynamic Power

VTC Curve

When the threshold voltage remain the same and the supply voltage drops lower, the overdrive voltage may become too sufficient resistance to be turned on. It would be switched off when it is needed to be switched on....
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