Booth Multiplier
Abstract
In this project an 8x8 multiplier was designed and simulated at the gate level and at the transistor level using the AMS simulator in Cadence Design System. We optimized the multiplier for speed by implementing fundamental building blocks directly in CMOS with the IBM CMRF7SF 0.18um process. Booth's multiplication algorithm was used to reduce the number of partial products, and thus the number of adders, providing a speed advantage. Furthermore, the adder circuit, which is the primary source of delay, was constructed with two layers of carry lookahead logic (CLA) to decrease propagation delay. A sign extension trick is utilized to further decrease the number of logic gates between the input and output. By using transistor level implementations for the CLA logic and the full adder, our design also reduces the total area required compared to gate level designs. Layout was constructed for each block and the full architecture. The worst case delay time with 100fF load capacitance was approximately 2.98ns. This propagation delay is 46% faster than the reference gate level design, where delay was 5.50ns. The final schematic consumes a total area less than 200x200 square microns. Total power consumption at an input signal rate of 200MHz was 2.5mW.
Gate Level Reference Design
A gate level implementation was designed and simulated as a reference design. A 100ps inverter delay was assumed in the Verilog functional description of the logic primitives. Using logical effort the delays of the remaining primitives were approximated. A detailed description of the original gate level design along with explainations of the Booth algorithm, the architecture, the logic equations used for this design, and other background information can be found in the following reports: Lab 3 Part II: Gate Level Booth Multiplier and Lab 3 Parts I&III: Logic Primitives.
Gate Level Booth Multiplier
The Booth multiplier functional simulation shows the simulation results of the gate
In this project an 8x8 multiplier was designed and simulated at the gate level and at the transistor level using the AMS simulator in Cadence Design System. We optimized the multiplier for speed by implementing fundamental building blocks directly in CMOS with the IBM CMRF7SF 0.18um process. Booth's multiplication algorithm was used to reduce the number of partial products, and thus the number of adders, providing a speed advantage. Furthermore, the adder circuit, which is the primary source of delay, was constructed with two layers of carry lookahead logic (CLA) to decrease propagation delay. A sign extension trick is utilized to further decrease the number of logic gates between the input and output. By using transistor level implementations for the CLA logic and the full adder, our design also reduces the total area required compared to gate level designs. Layout was constructed for each block and the full architecture. The worst case delay time with 100fF load capacitance was approximately 2.98ns. This propagation delay is 46% faster than the reference gate level design, where delay was 5.50ns. The final schematic consumes a total area less than 200x200 square microns. Total power consumption at an input signal rate of 200MHz was 2.5mW.
Gate Level Reference Design
A gate level implementation was designed and simulated as a reference design. A 100ps inverter delay was assumed in the Verilog functional description of the logic primitives. Using logical effort the delays of the remaining primitives were approximated. A detailed description of the original gate level design along with explainations of the Booth algorithm, the architecture, the logic equations used for this design, and other background information can be found in the following reports: Lab 3 Part II: Gate Level Booth Multiplier and Lab 3 Parts I&III: Logic Primitives.
Gate Level Booth Multiplier
The Booth multiplier functional simulation shows the simulation results of the gate