# Analogue Lab Report

Topics: Voltage, Electricity, High voltage Pages: 21 (2208 words) Published: October 10, 2013
﻿Introduction

FIGURE 1 : N-Channel JFET

The Junction Field Effect Transistor (JFET) is a three terminal device that consists of drain, source, and gate. The JFET is a voltage-controlled, constant-current device and a unipolar device. For this experiment, we used the JFET Self-bias circuit which in particular we use the n-channel. This kind of circuit is simple yet effective and is the most common biasing method for JFETs. The important thing to know is that the gate is essentially at 0V. When VDD increases, VDS also increases. Hence, the drain current, ID also will increase due to the increase of VDD. This increase in drain current is linear, because the depletion region is NOT large enough to have significant effect. If VGS is increased, depletion will be immediately generated in the channel so that the current required to pinch off the channel will be decrease. The voltage from power supply (VDD) provides the voltage across drain and source (VDS) to generate Id from drain to source for completion of the JFET operation method. When this happens, the drain current is form by flowing through the channel surrounding the p-type gates. The voltage across gate and source are provided by voltage source, VGG. The gate current will not be generated because of the voltage across gate and source is a reverse bias to the junction of gate source.

Figure of schematic diagram of the n-channel JFET

Formulas used:

Since IS=ID, VG= 0
VS=ISRS=IDRS
VG= -IDRS
VDS=VDD-IS(RS-RS)

Procedure

1) The circuit was connected as shown in Figure A. Two separate adjustable supplies (VGG and VDD) were used for the experiment. The grounds for both supplies were connected to the circuit ground.

2) The VDD was adjusted to 24V
A. With VDD = 24V, VGG was adjusted to 0V.
i) Measurements. Answers were recorded in Table 1
The Gate-Source voltage (VGS) and Drain-Source (VDS) were measured and recorded.

ii) Calculations. Answers were recorded in Table 1
The gate current (IG), where IG = (VGG – VGS)/ RS , the drain current (ID), where ID = (VDD-VDS)/ RD , and the emitter current (IS), where IS = ID+IG were all calculated.

B. With VDD = 24V, VGG was adjusted to -0.5V.
i) Measurements. Answers were recorded in Table 1
The Gate-Source voltage (VGS) and Drain-Source (VDS) were measured and recorded. ii) Calculations. Answers were recorded in Table 1
The gate current (IG), where IG = (VGG – VGS)/ RS , the drain current (ID), where ID = (VDD-VDS)/ RD , and the emitter current (IS), where IS = ID+IG were all calculated.

C. With VDD = 24V, VGG was adjusted to -1V, then to -1.5V, -2V until ID = 0A with increment of -0.5V i) Measurements. Answers were recorded in Table 1
The Gate-Source voltage (VGS) and Drain-Source (VDS) were measured and recorded. iii) Calculations. Answers were recorded in Table 1
The gate current (IG), where IG = (VGG – VGS)/ RS , the drain current (ID), where ID = (VDD-VDS)/ RD , and the emitter current (IS), where IS = ID+IG were all calculated.

3) VGG were adjusted to 0V
A. With VGG = 0V, VDD was adjusted to 0V.
iv) Measurements. Answers were recorded in Table 2
The Gate-Source voltage (VGS) and Drain-Source (VDS) were measured and recorded.

v) Calculations. Answers were recorded in Table 2
The gate current (IG), where IG = (VGG – VGS)/ RS , the drain current (ID), where ID = (VDD-VDS)/ RD , and the emitter current (IS), where IS = ID+IG were all calculated.

B. With VGG = 0V, VDD was adjusted to 1V.
i) Measurements. Answers were recorded in Table 2
The Gate-Source voltage (VGS) and Drain-Source (VDS) were measured and recorded. ii) Calculations. Answers were recorded in Table 2
The gate current (IG), where IG = (VGG – VGS)/ RS , the drain current (ID), where ID = (VDD-VDS)/ RD , and the emitter current (IS), where IS = ID+IG were all calculated.

C. With VGG = 0V, VDD was adjusted to 2V, then to 4,6,8,10,12,14,16,18,20,22 and 24V. i)...

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