For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT595 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state Product speciﬁcation Supersedes data of September 1993 File under Integrated Circuits, IC06 1998 Jun 04
8-bit serial-in/serial or parallel-out shift register with output latches; 3-state FEATURES • 8-bit serial input • 8-bit serial or parallel output • Storage register with 3-state outputs • Shift register with direct clear • 100 MHz (typ) shift out frequency • Output capability: – parallel outputs; bus driver – serial output; standard • ICC category: MSI. APPLICATIONS • Serial-to-parallel data conversion • Remote control holding register. DESCRIPTION
The 74HC/HCT595 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The “595” is an 8-stage serial shift register with a storage register and 3-state outputs. The shift register and storage register have separate clocks. Data is shifted on the positive-going transitions of the SHCP input. The data in each register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial standard output (Q7’) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. TYP. SYMBOL PARAMETER tPHL/tPLH propagation delay SHCP to Q7’ STCP to Qn MR to Q7’ fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑(CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V. maximum clock frequency SHCP, STCP input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 16 17 14 100 3.5 115 21 20 19 57 3.5 130 ns ns ns MHz pF pF HCT UNIT
1998 Jun 04
8-bit serial-in/serial or parallel-out shift register with output latches; 3-state ORDERING INFORMATION PACKAGE TYPE NUMBER NAME 74HC595N 74HC595D 74HC595DB 74HC595PW 74HCT595N 74HCT595D PINNING SYMBOL Q0 to Q7 GND Q7’ MR SHCP STCP OE DS VCC PIN 15, 1 to 7 8 9 10 11 12 13 14 16 DIP16 SO16 SSOP16 TSSOP16 DIP16 SO16 DESCRIPTION plastic dual in-line package; 16 leads (300 mil); long body plastic small outline package; 16 leads; body width 3.9 mm
VERSION SOT38-1 SOT109-1 SOT338-1 SOT403-1 SOT38-1 SOT109-1
plastic shrink small outline package; 16 leads; body width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm plastic dual in-line package; 16 leads (300 mil); long body plastic small outline package; 16 leads; body width 3.9 mm
DESCRIPTION parallel data output ground (0 V) serial data output master reset (active LOW) shift register clock input storage register clock input output enable (active LOW) serial data input positive supply voltage
12 9 15 1 2 3 4 5 6 7
Q1 1 Q2 2 Q3 3 Q4 4 Q5 5 Q6 6 Q7 7 GND 8
16 VCC 15 Q0 14 DS 13 OE
SHCP STCP Q7' Q0 Q1 Q2 14 DS Q3 Q4 Q5 Q6 Q7 MR 10 OE 13...
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