4-Bit Ripple Adder Report
Final Project, 4-bit Ripple Carry Adder
1. Introduction
In this project, a 4 -bit ripple carry adder is designed by using dynamic Manchester carry chain. This adder should be designed in Cadence Virtuoso for both schematics and layout.
This adder has 9 inputs, A0~A3, B0~B3 and CLK. When the design is finished, it should be checked in HSPICE for the functionality correctness. The worst case delay in this adder should be found by HSPICE as well.
2. Design
The figure shown below is the schema tics of dynamic carry chain.
Figure 1 Manchester Carry Chain
.
A
B
������������
S
������������
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
Table 1 Full Adder Truth Table
From the truth table of full adder, the functions of P and G are easily to get
P =A ⊕ B
G =AB
The formula below shows the sum bit.
S (G, P) = ( A ⊕ B) ⊕ ������������
S (G, P) = P ⊕ ������������
3. Schematics
From the schematics and formula shows above, an Inverter, AND gate and XOR gate should be designed to finish the 4 -bit ripple carry adder using Manchester carry chain.
Inverter
An inverter uses one NMOS transistor a nd one PMOS to implement.
The figure below shows schematics of inverter.
Figure 2 Inverter
AND Gate
An NAND gate and an Inverter can construct a AND gate. An AND gate need 6 transistors in total. In the dynamic manchester carry chain, G is a and gate. The figure below is an AND gate; G = AB.
Figure 3 AND Gate
XOR Gate
In this XOR gate design, transmission gate is used to implement the XOR gate.
There are only 6 transistors to implement XOR gate using transmission gate while the CMOS XOR gate needs 12 transistors. The figure below shows the XOR gate.
In
this
transmission
XOR gate,
an
inverter
Figure 4 XOR gate
needed to implement B
1. Introduction
In this project, a 4 -bit ripple carry adder is designed by using dynamic Manchester carry chain. This adder should be designed in Cadence Virtuoso for both schematics and layout.
This adder has 9 inputs, A0~A3, B0~B3 and CLK. When the design is finished, it should be checked in HSPICE for the functionality correctness. The worst case delay in this adder should be found by HSPICE as well.
2. Design
The figure shown below is the schema tics of dynamic carry chain.
Figure 1 Manchester Carry Chain
.
A
B
������������
S
������������
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
Table 1 Full Adder Truth Table
From the truth table of full adder, the functions of P and G are easily to get
P =A ⊕ B
G =AB
The formula below shows the sum bit.
S (G, P) = ( A ⊕ B) ⊕ ������������
S (G, P) = P ⊕ ������������
3. Schematics
From the schematics and formula shows above, an Inverter, AND gate and XOR gate should be designed to finish the 4 -bit ripple carry adder using Manchester carry chain.
Inverter
An inverter uses one NMOS transistor a nd one PMOS to implement.
The figure below shows schematics of inverter.
Figure 2 Inverter
AND Gate
An NAND gate and an Inverter can construct a AND gate. An AND gate need 6 transistors in total. In the dynamic manchester carry chain, G is a and gate. The figure below is an AND gate; G = AB.
Figure 3 AND Gate
XOR Gate
In this XOR gate design, transmission gate is used to implement the XOR gate.
There are only 6 transistors to implement XOR gate using transmission gate while the CMOS XOR gate needs 12 transistors. The figure below shows the XOR gate.
In
this
transmission
XOR gate,
an
inverter
Figure 4 XOR gate
needed to implement B