Signal Integrity
Signal Integrity Considerations for High Speed Digital Hardware Design White Paper
Issue: 01, 11th November 2002 Mick Grant, Design Engineer
Abstract As system clock frequencies and rise times increase, signal integrity design considerations are becoming ever more important. Unfortunately many Digital Designers may not recognise the importance of signal integrity issues and problems may not be identified until it is too late. This paper presents the most common design issues affecting signal integrity in high-speed digital hardware design. These include impedance control, terminations, ground/power planes, signal routing and crosstalk. Armed with the knowledge presented here, a digital designer will be able to recognise potential signal integrity problems at the earliest design stage. Also, the designer will be able to apply techniques presented in this paper to prevent these issues affecting the performance of their design.
1
Introduction
Despite the fact that Signal Integrity (SI) is among the most fundamental of design practices for hardware engineers, the digital design community has long ignored it. Through the age of low-speed logic, designing for SI was considered wasted effort, as the probability of SI-related issues was low. However as clock rates and rise times increased through the years, the need for SI analysis and design also increased. Unfortunately many designers have not heeded the call and still neglect to consider SI in their designs. Modern digital circuits can operate up to gigahertz frequencies with rise times in the order of fifty picoseconds. At these speeds, a carelessly designed PCB trace only needs to be an inch or so long before it radiates. Radiating traces create voltage, timing and interference problems not only on that line, but also across the entire board and even across adjacent boards. The problem is even more critical with mixed-signal circuits. For example, consider a system that relies upon a high-performance ADC to
Issue: 01, 11th November 2002 Mick Grant, Design Engineer
Abstract As system clock frequencies and rise times increase, signal integrity design considerations are becoming ever more important. Unfortunately many Digital Designers may not recognise the importance of signal integrity issues and problems may not be identified until it is too late. This paper presents the most common design issues affecting signal integrity in high-speed digital hardware design. These include impedance control, terminations, ground/power planes, signal routing and crosstalk. Armed with the knowledge presented here, a digital designer will be able to recognise potential signal integrity problems at the earliest design stage. Also, the designer will be able to apply techniques presented in this paper to prevent these issues affecting the performance of their design.
1
Introduction
Despite the fact that Signal Integrity (SI) is among the most fundamental of design practices for hardware engineers, the digital design community has long ignored it. Through the age of low-speed logic, designing for SI was considered wasted effort, as the probability of SI-related issues was low. However as clock rates and rise times increased through the years, the need for SI analysis and design also increased. Unfortunately many designers have not heeded the call and still neglect to consider SI in their designs. Modern digital circuits can operate up to gigahertz frequencies with rise times in the order of fifty picoseconds. At these speeds, a carelessly designed PCB trace only needs to be an inch or so long before it radiates. Radiating traces create voltage, timing and interference problems not only on that line, but also across the entire board and even across adjacent boards. The problem is even more critical with mixed-signal circuits. For example, consider a system that relies upon a high-performance ADC to
References: [1] High Speed Digital Design: A Handbook of Black Magic, Johnson H and Graham M, 1993, Prentice-Hall PTR, Upper Saddle River, NJ, USA [2] Differential Signals: Rules to Live By, Brooks D, 2001, Taken from http://www.ultracad.com/differentialrules.com Document Number CAL-000002-WP-01 12/12 Author Mick Grant