Novel On Chip-Interconnect Structure for Giga-Scale Integration VLSI ICs Usha Rani.Nelakuditi, S.Niranjan Reddy Dept. of ECE, Vignan University Vadlamudi, Guntur-522 213, A.P., India email@example.com, firstname.lastname@example.org
Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements. Keywords : Interconnect structure, WPM Routing Technique, Distributed resistance, Timing Constraints, power, area performance .
of equi-spaced repeaters. Hence for the wide range of interconnects to improve the interconnect design, the Wave Pipelined Multiplexed (WPM) routing technique can be used. This WPM routing technique[1,2,3] takes the advantage of intra-clock idleness and transmits multiple data signals over the interconnect in a wave-pipelined fashion. This WPM routing technique can be used two terminal nets. In this paper the performance of WPM interconnect structure is thoroughly analyzed and the performance is compared with the conventional method. In this paper section1 discusses the introduction, section2 various interconnection structures are discussed, section3 implementation of these methods in VLSI is discussed and section4 discusses the simulation results and conclusions.
2. Interconnection Structures
In this section the two kinds of interconnection structures are discussed. In the conventional method each source and sink are connected by using a dedicated interconnect wire. To connect ‘n’ sources with ‘n’ sinks ‘n’ interconnect wires are required. As shown in Figure.1.conventional method needs two dedicated lines to connect two sources with two sinks. Input pipelined register 1 Output pipelined register 1
Now-a-days people are using high density C-MOS SOCs and IP Cores to realize their applications with in the short time. As density increases interconnections between the logic becomes a tedious task. Hence to improve the system performance as well as to meet market needs a novel method is considered which improves the overall system performance by reducing the interconnect delay. This method not only reduces the complexity that is present in the interconnects and also reduces the unwanted parasitic parameters. Various solutions have been existed to solve this interconnect problem. Repeater insertion is one of the most commonly adopted strategies to reduce the interconnect delay. As chip density is drastically increasing it is difficult to insert an optimal number Input pipelined register 2
Dedicated interconnects CLK Output pipelined register 1
Figure.1. Conventional Routing Technique
The ever-increasing transistor count in current and future digital systems has made necessary to have a large number of...
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