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  • Topic: Electronic design automation, Integrated circuit, Logic gate
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Lecture 0

VLSI Design
Introduction to the subject
Rajesh Ghongade VIIT

• Teaching Scheme
– Lectures: 3 Hrs/week – Practical: 2 Hrs/Week

• Examination Scheme
– Paper: 100 Marks – Practical: 50 Marks – Oral: 25 Marks

VHDL Modeling and Design Flow Introduction to VLSI: complete VLSI design flow (with reference to an EDA tool). Sequential, Data flow, and Structural Modeling. Functions. Procedures, attributes. Test benches, Synthesizable, and non synthesizable statements; packages and configurations Modeling in VHDL with examples of circuits such as counters, shift registers, bidirectional bus, etc.

Unit 2
FSM And Sequential Logic Principles Sequential Circuits, Meta-stability Synchronization, Design of Finite State Machines, and State minimization, FSM CASE STUDIES - Traffic Light control. Lift Control and UART STA and DTA

Unit 3
Programmable Logic Devices Introduction to the CPLDs, Study of architecture of CPLD. and Study of the Architecture of FPGA

Unit 4
System On Chip One, two phase clock, Clock distribution. Power distribution. Power optimization, SRC and DRC, Design validation, Global routing, Switch box routing. Off chip connections, I/O Architectures, Wire parasitics, EMI immune design. Study of memory-Basics of memory includes types of memory cells and memory architectures. Types of memory, based on architecture specific and application specific viz. SRAM, DRAM, SDRAM, FLASH, FIFO.

Unit 5
CMOS VLSI CMOS parasitics, equivalent circuit, body effect, Technology Scaling, A. parameter. Detail study of Inverter Characteristics, power dissipation, power delay product, CMOS combinational logic design and W/L calculations. Transmission gates, Introduction to CMOS layout.

Unit 6
Testability Need of Design for testability, Introduction to Fault Coverage, Testability. Design- forTestability, Controllability and Observability, Stuck-at Fault Model. Stuck-Open and Stuck-Short faults. Boundary Scan check. JTAG technology; TAP Controller and TAP Controller State Diagram. Scan path. Full and Partial scan. BIST

Text Books
1. John F. Wakerly, "Digital Design, Principles and Practices", Prentice Hall Publication 2. Neil H. E Weste and Kamran Eshraghian, "Principles of CMOS VLSI Design". 3. Wayne Wolf, "Modern VLSI Design" 4. Sudhkar Yalamachalli, "Introductory VHDL from simulation to Synthesis"

Reference Books
1. 2. 3. 4. 5. 6. 7. 8. Perry "VHDL" Charles Roth, "Digital System Design using VHDL". McGraw hill. Xilinx Data Manual "The Programmable Logic Data Book". Stephen Brown and Zvonko Vranesic, "Fundamentals of Digital Logic with VHDL Design", Second Edition, McGraw-Hill, 2005. Michael John Sebastian Smith, "Application-Specific Integrated Circuits", Addison Wesley. Wayne Wolf, "FPGA-Based System Design", Prentice Hall, Miron Abramovici, "Digital Systems Testing and Testable Design", Jaico Publishing. Sung-Mo (Steve) kang, Yusuf Leblebici, " CMOS Digital Integrated Circuit", Tata McGraw-Hill Publication.

Any 8 assignments out of the following: Simulation, Synthesis, and Implementation of: 1. 8: 1 Multiplexer, 2:4 Decoder, Comparator and Adder. 2. Flip Flop, Shift Register and Counter 3. Lift Controller /Traffic Light Controller/ UART. Anyone of the three. 4. Parity generator and Checker. 5. Implementation of RAM/FIFO. 6. Ramp waveform generator using DAC 7. Bi-directional buffer 8. Temperature sensing using ADC, Displaying on 7-Segment display and threshold setting using keyboard 9. Implementation of 4-bit RISC processor

EDA Tools
• Active-HDL 6.3 sp1
– (VHDL compiling and simulation)

• Synpilfy Pro 8.2
– Synthesis

• Xilinx Webpack 8.X
– Implementation

Alternate EDA Tools
• Libero Gold 6.2
– (VHDL compiling & implementation)

• Modelsim 6.0
– Simulation

• Synpilfy 8.2
– Synthesis

Hardware available
• • • • Actel ProASIC PLUS evaluation board with APA300-PQ208 device Xilinx CPLD Dedicated Trainer XC 9572 PC 84 Xilinx FPGA...
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