IB\I, System Products Division and IT, ECAE, Bocblingen, Federal Republic of Germany
Abstract: Potentially, the silicon based VLSI chip packaging and interconnection technology (Hybrid Wafer-Scale Integration = II-WSI) provides for several thousands of high-speed interconnections between individual VSLl chips, allowing an electrically homogeneous, chip-boundary transparent clustering of a tremendous amount of digital circuitry. Therefore, the abstract structured logic design methodology may also be efficiently used for more complex system structures, such as an entire central electronic complex (CEC) of a supermini-computer w h c h may comprise a multitude of VLSI chips executing heterogeneous system functions. The brief introduction concerning an abstract structured digital design utiL i n g increased intercommunication resources between functional logic modules is followed by a description of several potential realkation concepts of the silicon based VLSI chip interconnection technology which provides extraordinarily high pin count. In addition, the key aspects of the silicon based interconnection technology are outlined and their potential use in sy5tem level design is illustrated by several intercommunication intensive implementation examples. Introduction \\.'bile advocating silicon based VLSI chip packagjng and interconnection tcchnologq and various implementation alternatives thereof, one is often confronted with the question what the system design related aspects and advantages of this technology really are.
tion is constructed b) mterconnecting a multitude of ”simplest fragments” according to certain rules. This seems to be a natural method which is also used by logic designers to subdivide a given overall control process into mdividual fragments, considering the specified process functions and the available or chosen generic hardware and progam r e k a t i o n (abstract structuring into functional modules such as microscquencers, ALLs, etc.), while divegarding the hardu-are partitioning onto the individual physical components. 1.or each fragment built by connecting other fragments both an initial and a final state are determined. Ihercforc, each newl) built fragment can participate in forming consecutive structured elements hierarchically. The fragments may- be connected by the basic operations listed below and shown in rig. Ib:
Connection in the form of (cascddcd) chain5 (serial compovtion): ‘I he new fragment S = SAx Sg is obta~nedb) chaining fragments .SA and CB such that the initial state of S cquals the imtial state of .SA and the final statc of S equals the fmal state of SE. Connection in the form of parallel branches (parallel composition): I he ncw l r a p c n t S = S,v.S, is obtained b connecting fragments SA ! and Sg such that the initial state of S equals the initial states of both SA and .Sa and the final \taw of S equals thc final states of both SA and SB. Connection in the form of loops (c!clic composition): I h i s operation Ls a cipgle-placed one. The resulting fragment S, denoted as S = SA or C(S,), is derived from SA by superposing its mitial and fmal states to obtain one state that is declared to be the common initial and final state of S .
In complex system realizations, the most difficult design problem still I S thc mapping (partitioning) of the functionally required logic onto existing phbsical circuit components (VLSI chips) which currently offer a v e v limited number of interconnections (pins). Traditionally, s) stem designers are nell-trained to circumvent the problem of an insufficient number of interconnections between individual ph) sical units (VLSI chips) by various signal multiplexing techniques in order to intuitively resolve the problem of physical partitioning and placement of the...