Vhdl Project Report

Only available on StudyMode
  • Download(s) : 515
  • Published : October 15, 2012
Open Document
Text Preview
Design of Quantizer with Signed Quantization Level (3 downto -4)

Mini Project Report
VHDL and Digital Design

Table of Contents
| | Page No|
1| Introduction| 4|
| 1.1| Fixed Point Package | 5|
| 1.2| IEEE floating-point representations of real numbers| 5| | 1.3| Results & Discussion| 8|
2.| Conclusion| 20|
| Bibliography| 20|
Appendix A:| |
| VHDL Test Bench code Quantizer with Signed Quantization Level (3 downto -4)| 21|

List of Figures:
Figure 1 : | Block Diagram of Complete Simulation Model| Figure 2:| Binary to Octal Encoder and corresponding decoder system| Figure 3:| Xilinx ISE simulator’s testbech waveform output for a real value input 2.93893|

Chapter 1
Introduction
In this work we have designed a digital 8-bit quantizer to reduce the number of bits involved in representing a real valued sample to a fixed point representation with reduced number of bits. The work also involved designed of a Binary to Octal encoder and corresponding decoder. The implementation of encoder-decoder involved conversion of the Fixed point number to Standard Logic vector. After the encoding and decoding process the Slandered Logic vector is converted back to Fixed point number then back to Real Number representation. Quantization error is calculated form the difference between input and output real numbers. We have utilized Xilinx ISE simulator and IEEE proposed Fixed Point package during execution of the projects. Figure 1 shows the block diagram representation of the proposed system.

INPUT
(Type: Real)
Sample Values
Real To Fixed Point Conversion
Signed Quantization Level (3 downto -4)
Resolution (0.0625)
Fixed Point to
IEEE Standard Bit Vector Conversion
Hex Encoding
Binary to Octal Encoding / Encryption
Hex Encoding
Octal to Binary Decoding / Decryption
Hex Encoding
IEEE Standard Bit Vector to Fixed Point Conversion
Fixed Point To
Conversion
Real Type Conversion
Conversion
Error Calculation

Figure 1: Block Diagram of Complete Simulation Model

1.1 Fixed Point Package :
Fixed point is a step between integer math and floating point. This has the advantage of being almost as fast as numeric_std arithmetic, but able to represent numbers that are less than 1.0. A fixed-point number has an assigned width and an assigned location for the decimal point. As long as the number is big enough to provide enough precision, fixed point is fine for most DSP applications. Because it is based on integer math, it is extremely efficient, as long as the data does not vary too much in magnitude. This package defines two new types: “ufixed” is the unsigned fixed point, and “sfixed” is the signed fixed point. 1.2 IEEE floating-point representations of real numbers

No human system of numeration can give a unique representation to every real number; there are just too many of them. So it is conventional to use approximations. For instance, the assertion that pi is 3.14159 is, strictly speaking, false, since pi is actually slightly larger than 3.14159; but in practice we sometimes use 3.14159 in calculations involving pi because it is a good enough approximation of pi. One approach to representing real numbers, then, is to specify some tolerance epsilon and to say that a real number x can be approximated by any number in the range from x - epsilon to x + epsilon. Then, if a system of numeration can represent selected numbers that are never more than twice epsilon apart, every real number has a representable approximation. For instance, in the United States, the prices of stocks are given in dollars and eighths of a dollar, and rounded to the nearest eighth of a dollar; this corresponds to a tolerance of one-sixteenth of a dollar. In retail commerce, however, the conventional tolerance is half a cent; that is, prices are rounded to the nearest cent. In this case, we can represent a sum of money as an whole number of cents, or...
tracking img