ELE591 - VHDL for Synthesis
Issue 1.0: 1st December 2010
The purpose of this laboratory experiment is to familiarise you with the principles of VHDL for synthesis targeted at programmable logic devices. You will observe how various VHDL descriptions result in Register Transfer Level (RTL) implementations and how these can be implemented within specific logic devices. The principles of back-annotation will also be explored and how this can be used to examine performance limitations of specific hardware resource mappings.
This lab assumes you are already familiar with Xilinx ISE and ModelSim, given that ELE335 is a prerequisite for this module. If necessary, consult the ELE335 lab guide, which is included in the Coursework section of the ELE591 module webpage. Most of the VHDL files needed for this lab are also available from the same location.
Aim: To compare the results of different architectural descriptions for the same entity Steps:
• Create a project named “exercise1”. Add the file ex1a.vhd as a “VHDL module” • Select the Spartan3 as the target device
• Compile and synthesise the VHDL description and examine the design report file, paying particular attention to the resource utilisation summary (and timing path analysis). Also examine the RTL design. • Repeat with the files ex1b.vhd and ex1c.vhd and compare the results.
Aim: To illustrate the use of “don’t care” values in synthesis Steps:
• Create a project named “exercise2”. Add the file docare.vhd as a “VHDL module” • Compile and synthesise the design targeting the Spartan3 device • Add the file dontcare.vhd as a “VHDL module” and repeat the synthesis. • Compare the report files.
Aim: To illustrate logic resource requirements for conditional versus mutually exclusive input conditions Steps:
• Create a project named “exercise3”. Add the file cond.vhd as a “VHDL module” • Compile and synthesise the design...
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