Verilog - a Guide to Digital Design and Synthesis

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  • Topic: Electronic design automation, Verilog, VHDL
  • Pages : 95 (20589 words )
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  • Published : January 4, 2013
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Verilog HDL
A guide to Digital Design and Synthesis
Samir Palnitkar

SunSoft Press 1996

PART 1 BASIC VERILOG TOPICS 1 Overview of Digital Design with Verilog HDL 2 Hierarchical Modeling Concepts 3 Basic Concepts 4 Modules and Ports 5 Gate-Level Modeling 6 Dataflow Modeling 7 Behavioral Modeling 8 Tasks and Functions 9 Useful Modeling Techniques PART 2 Advance Verilog Topics 10 Timing and Delays 11 Switch- Level Modeling 12 User-Defined Primitives 13 Programming Language Interface 14 Logic Synthesis with Verilog HDL PART3 APPENDICES A Strength Modeling and Advanced Net Definitions B List of PLI Rountines C List of Keywords, System Tasks, and Compiler Directives D Formal Syntax Definition E Verilog Tidbits F Verilog Examples

1 3 11 27 47 61 85 115 157 169 191 193 213 229 249 275 319 321 327 343 345 363 367

Part 1 Basic Verilog Topics


Overview of Digital Design with Verilog HDL Evolution of CAD, emergence of HDLs, typical HDL-based design flow, why Verilog HDL?, trends in HDLs. Hierarchical Modeling Concepts Top-down and bottom-up design methodology, differences between modules and module instances, parts of a simulation, design block, stimulus block. Basic Concepts Lexical conventions, data types, system tasks, compiler directives.

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Modules and Ports Module definition, port declaration, connecting ports, hierarchical name referencing. Gate-Level Modeling Modeling using basic Verilog gate primitives, description of and/or and buf/not type gates, rise, fall and tum-off delays, min, max, and typical delays. Dataflow Modeling Continuous assignments, delay specification, expressions, operators, operands, operator types. Behavioral Modeling Structured procedures, initial and always, blocking and nonblocking statements, delay control, event control, conditional statements, multiway branching, loops, sequential and parallel blocks. Tasks and Functions Differences between tasks and functions, declaration, invocation.

Useful Modeling Techniques Procedural continuous assignments, overriding parameters, conditional compilation and execution, useful system tasks.

Verilog HDL: A Guide to Digital Design and Synthesis

Overview of Digital Design

with Verilog® HDL

1.1 Evolution of Computer Aided Digital Design
Digital circuit design has evolved rapidly over the last 25 years. The earliest digital circuits were designed with vacuum tubes and transistors. Integrated circuits were then invented where logic gates were placed on a single chip. The first integrated circuit (IC) chips were 55I (Small Scale Integration) chips where the gate count was very small. As technologies became sophisticated, designers were able to place circuits with hundreds of gates on a chip. These chips were called M5I (Medium Scale Integration) chips. With the advent of LSI (Large Scale Integration), designers could put thousands of gates on a single chip. At this point, design processes started getting very complicated, and designers felt the need to automate these processes. Computer Aided Design (CAD)1 techniques began to evolve. Chip designers began to use circuit and logic simulation techniques to verify the functionality of building blocks of the order of about 100 transistors. The circuits were still tested on the breadboard, and the layout was done on paper or by hand on a graphic computer terminal. With the advent of VLSI (Very Large Scale Integration) technology, designers could design single chips with more than 100,000 transistors. Because of the complexity of these circuits, it was not possible to verify these circuits on a breadboard. Computer-aided techniques became critical for verification and design of VL5I digital circuits. Computer programs to do automatic placement and routing of circuit layouts also became popular. The designers were now building gate-level digital circuits manually on graphic terminals. They would build small building blocks and then derive higher-level...
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