TSMC's program is aimed to reduce development cycles and manufacturing costs, according to analysts. But it could also possibly cause a major stir in the industry, as the silicon foundry giant wants more of the IC pie and appears to be encroaching on the turf in the third-party EDA, IP, packaging and test communities.
As part of its strategy, TSMC is quietly pushing a concept called the Open Innovation Platform (OIP), according to Gartner Inc. During its technology conference last week, TSMC also disclosed details about its roadmap in the chip-packaging front, including its internal efforts in the 3D arena.
OIP is a program that involves more "collaboration between the foundry and its clients at the early stages of the design phase," said Jim Walker, an analyst with Gartner, in an e-mail newsletter.
TSMC's OIP consists of a platform of design tools and IP to help customers with their design-to-manufacturing efforts, Walker said. "OIP integrates TSMC's manufacturing technologies, silicon IP, massive manufacturing database and compatible third-party silicon IP and design tools," he said.
"Through OIP, TSMC can offer vertically integrated services, from designing and manufacturing to testing and packaging, thus shortening clients' IC development processes and reducing their manufacturing costs," he said.
Concern for competitors
Many of these efforts could be viewed as competitive to TSMC's current partnerships in the EDA, IP and IC-packaging communities. For example, "this announcement should be of concern to the SATS industry companies (that is, contract assembly and test houses), such as Amkor Technology, Advanced Semiconductor Engineering, Siliconware Precision Industries Ltd, STATS ChipPAC, UTAC and others," Walker wrote. "This expansion in services...