IEEE TRANSACTIONS ON COMPUTERS
Trafﬁc-aware Design of a High Speed FPGA
Network Intrusion Detection System
Salvatore Pontarelli, Giuseppe Bianchi, Simone Teoﬁli
Consorzio Nazionale InterUniversitario per le Telecomunicazioni (CNIT)
University of Rome “Tor Vergata”
Via del Politecnico 1, 00133, Rome, ITALY
Abstract—Security of today’s networks heavily rely on Network Intrusion Detection Systems (NIDSs). The ability to
promptly update the supported rule sets and detect new emerging
attacks makes Field Programmable Gate Arrays (FPGAs) a
very appealing technology. An important issue is how to scale
FPGA-based NIDS implementations to ever faster network links.
Whereas a trivial approach is to balance trafﬁc over multiple,
but functionally equivalent, hardware blocks, each implementing
the whole rule set (several thousands rules), the obvious cons
is the linear increase in the resource occupation. In this work,
we promote a different, trafﬁc-aware, modular approach in the
design of FPGA-based NIDS. Instead of purely splitting trafﬁc
across equivalent modules, we classify and group homogeneous
trafﬁc, and dispatch it to differently capable hardware blocks,
each supporting a (smaller) rule set tailored to the speciﬁc trafﬁc
category. We implement and validate our approach using the
rule set of the well known Snort NIDS, and we experimentally
investigate the emerging trade-offs and advantages, showing
resource savings up to 80% based on real world trafﬁc statistics
gathered from an operator’s backbone.
Index Terms—Deep Packet Inspection, FPGA, Intrusion Detection System, Snort, String matching, Trafﬁc awareness
I. I NTRODUCTION
The demand for network security and protection against
threats and attacks is ever increasing, due to the widespread
diffusion of network connectivity... [continues]
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