Thyristor Ram

Only available on StudyMode
  • Topic: Bipolar junction transistor, Static random access memory, Dynamic random access memory
  • Pages : 5 (1615 words )
  • Download(s) : 392
  • Published : March 6, 2012
Open Document
Text Preview
THYRISTOR RAM
Muktesh Waghmare, Raman Gaikwad

1: Principle:
Thyristor is well-known for its high-current drive capability and its bi-stable characteristics. It has been widely used in power electronics applications. With the exponential advances in CMOS technology tiny thyristor devices can now be easily embedded into conventional nano-scale CMOS. This enables the creation of a memory cell technology with features that include small cell size, high performance, reliable device operation, and good scalability. Use of thyristor provides a positive regenerative feedback that results in very large bit cell operation margins. The difference is that the four-transistor CMOS latch of a 6T-SRAM is replaced by the PNP-NPN bipolar latch of a single thyristor device, which reduces cell area dramatically and enables high-density macros.

2: Need of the technology:

There has always existed a fundamental performance-density trade-off between SRAM and DRAM, the only two commercially viable volatile memory technologies. SRAM provides high performance at the expense of a large cell area, while DRAM provides high density but with low performance. The internal latch of a SRAM cell comprises of four-six transistors. This degrades the packaging density of a SRAM based memory. The performance limitation of DRAM is primarily a result of using a passive capacitor as the storage device without an internal gain. DRAM read operation is therefore destructive and the data retention is highly leakage sensitive. Destructive read requires the use of a read and write-back operation for every memory access or refresh operation, slowing down the random cycle time. Since a T-RAM cell consists of only two elements (a thyristor device and an access FET), its cell area is significantly smaller than 6T SRAM. The slow turn-off speed of a conventional thyristor is addressed in a T-RAM cell through the use of a thyristor structure, called thin capacitively coupled thyristor TCCT).

3: Working:
The fundamental component of a thyristor based cell structure is the internal thyristor latch. A CMOS-based thyristor device known as a Thin Capacitively Coupled Thyristor (TCCT) (Fig.1) has been introduced as a novel switching device for high-density high-performance memory applications in thyristor based memory cells.

The switching speed of the TCCT device is determined by various device parameters such as npn and pnp bipolar gains, gate to-p base capacitive coupling ratio, and carrier lifetime τ in J1. Due to the unique gate coupling mechanism, the excess carriers in the p-base are removed at the falling edge of the gate pulse without carrier recombination; however, carriers in the n-base need to be removed by recombination. Therefore, the carrier lifetime in the J1 junction becomes a limiting factor for the turn-off switching speed. When τ is reduced, carriers in the n-base are more quickly recombined, resulting in improved turn-off speed. [3]

The switching speed of the TCCT device is determined by various device parameters such as npn and pnp bipolar gains, gate to-p base capacitive coupling ratio, and carrier lifetime τ in J1. Due to the unique gate coupling mechanism, the excess carriers in the p-base are removed at the falling edge of the gate pulse without carrier recombination; however, carriers in the n-base need to be removed by recombination. Therefore, the carrier lifetime in the J1 junction becomes a limiting factor for the turn-off switching speed. When τ is reduced, carriers in the n-base are more quickly recombined, resulting in improved turn-off speed. The gain of bipolar transistors increases with temperature. Indium is employed as the p-base dopant species in order to modulate the temperature coefficient of NPN gain and stabilize thyristor characteristics over a wide operating temperature range. The base of an NPN bipolar transistor is typically doped...
tracking img