Some Important terms:
1) HDL: Hardware Description Language
e.g. VHDL and Verilog
This is the language in which the design is coded. The design code is in a specific format called RTL design.
2) RTL: Register Transfer Logic
The way the design is coded.
2a) flip flop: One unit for 1 memory retention.
3) Test bench: This is the program that tests the design. It applies the stimulus to the design and compares the actual output with the expected output. If the actual output is same as the expected output then the test case passes i.e the functionality is correct. If the actual output is different then the expected output then there is a bug which has to be fixed by the designer of the module which is not behaving the way it should. The expected output is obtained by applying the test case to the C model of the ASIC.
3 a) HVL: Hardware Verification Language
The testbench required to test the RTL design is coded using HVL. Examples are (VERA, e language and system C).
The complex testbenches like the full chip verification is normally written in HVL. Prior to the use of HVL, HDLs were used to write the simple testbenches. As the complexity of testbench increases with the increase in the design and functionality HVL are being used to write complex testbenches.
4) Module level Verification:
Each RTL designer codes his module/ modules. He writes a small testbench to test his module so that the bugs caught are fixed at the module level. This verification is called module level verification
5) Chip level Verification
Once all the module are tested separately then One engineer with integrate all the modules into chip level design. This chip level design it tested by instantiated it in the chip level verification environment. This environment can be coded in VERA, E language and /or system C or system verilog.
The verification is an iterative process where the testcases are applied and the response viewed. Incase any bug then the bug is fixed in the corresponding module and the verification test cases are run again. This is performed until all the test case passes on a particular version of the design.
VERA is from Synopsys and e language is from Cadence
6) EDA: Electronic Design Automation:
Companies that provide tools for the VLSI industry. The three biggest and major companies are
Synopsys: Turnover 1.5 to 1.6 Billion US Dollars
Cadence: Turnover 1.2 to 1.3 Billion US Dollars
Mentor Graphics: Turnover 0.9 to 1 billion US Dollars.
All three are US based Companies. There are other small companies but are not too many. Automation provided to make electronic design automated.
7) ASIC: Application Specific Integrated Circuits:
These Integrated Circuits are designed by many many fabless companies. Fabless companies are those who do not have there fabrication Facilities. Many third party fabrication companies develop the ASIC from the mask. Mask is the final output of the VLSI design which is given to the fab. ICs designed for a particular application are known as the ASIC.
8) SoCs: System on chip
The full system which use to be on the board is now designed on a chip means single IC. This has resulted in miniaturization of the electronic products like mobiles, telephones, telecommunications and also all the electronic products which involves semiconductors.
Use to be sold as ICs like Intel Pentium or core duo processors, etc. These microprocessors are also available as soft core which can be integrated into SoCs. Microprocessors are like the brain of the computer where all the computation happens.
10) VLSI: Very large scale integration
This includes Micro Electronics and nano technologies. Microelectronic is when the transistor size is fabricated in micron e.g. 0.18u, 0.36 micron. With new technologies the transistor can now be fabricated in 30 nano, 45 nano, 65 nano and 90 nano.
One micron is 10 raised to -6. One...
Please join StudyMode to read the full document