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Topics: CPU cache, Real-time computing, Computer Pages: 66 (18227 words) Published: March 13, 2013
Instruction Cache Memory Issues in Real-Time Systems
Filip Sebek
Computer Architecture Lab Department of Computer Science and Engineering Technology licentiate thesis 2002-10 ISBN 97-88834-38-7 (13th September 2002)

Instruction Cache Memory Issues in Real-Time Systems
Filip Sebek

Department of Computer Science and Engineering Mälardalen University Västerås, Sweden

Cache memories can contribute to significant performance advantages due to the gap between CPU and memory speed. They have traditionally been thought of as contributors to unpredictability because the user can not be sure of exactly how much time will elapse while a memory-operation is performed. In a real-time system, the cache memory may contribute to a missed deadline by actually making the system slower, but this is rare. To avoid this problem, the developers of real-time systems have run the program in the old-fashioned way; with disabled cache — just to be safe. Turning the cache off, however, will also make other features like instruction pipelining less beneficial so the new processors will not give the performance speedup as they were meant to give. The first methods to determine the boundaries of the execution time in computer systems with cache memories were presented in the late eighties — twenty years after the first cache memories were designed. Today, fifteen years later, further methods have been developed to determine the execution time with cache memories . . . that were state-of-the-art fifteen years ago. This thesis presents a method of generating worst-case execution time scenarios and measure the execution time during those. Several important properties can be measured. These include cache-related pre-emption delay, missratio levels of software, and instruction cache miss-ratio threshold levels for increased system performance. Besides the dynamic measurement method, a statical procedure to determine the maximum instruction cache miss-ratio level is presented. Experimental results from this research show that the indirect cache cost of a pre-emption is very high — more than three times the execution cost of the context-switch functions themselves. Another result shows that the tested computer system without caching will not cause a missed deadline if the instruction cache is enabled. i


Copyright c Filip Sebek, 2002 ISBN 97-88834-38-7 Printed by Arkitektkopia, Västerås, Sweden Distribution: Mälardalen University Press A This document was written in Emacs 20.3.1, typesetted in LTEX, spell and grammar checked in Microsoft Word 2000 and compiled with MikTeX 2.2. Figures were created by gpic from the GNU organization and dot from AT&T labs.

To Linda, Zacharina, and Xerxes

It all began that day in 1981 when my father came home with the book “Basic Basic” by Dag Toijer which he had borrowed from the library. I read the book several times and started to write programs — with a paper and pen since a computer was far too expensive to own. Four years later I bought my first computer — a Commodore 64. I will never forget that day in Hanover, walking proudly with the box containing my very own computer. Many books and computers later, in 1998, I had the opportunity to become a Ph.D. student while working as a teacher at Mälardalen University. The Department of Computer Engineering performed research in real-time systems, and since my main interest was in computer architecture, I found this combination of topics to be natural but also very exciting. It has been a challenge to struggle with unreadable papers, bugs in my own software, and glitching hardware not to mention all the other duties I have as a teacher and being a part of my own family. Several times I have been close to giving it all up, but today I’m finally there. The work presented in this thesis would probably have been impossible if I had not had such encouraging and stimulating people around me. My supervisors Lennart Lindh, Björn Lisper, Hans...
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