SiGe BiCMOS Technology for Communication Products
Marco Racanelli and Paul Kempf
4321 Jamboree Rd, Newport Beach, CA 92660
SiGe BiCMOS technology is reviewed with focus on recent
advances including the achievement of >200 GHz Ft and
Fmax SiGe transistors, integration with generic 0.13 µm
CMOS, and the realization of low-cost nodes for the
integration of wireless transceivers.
wireless and wire-line circuit examples are also provided.
SiGe BiCMOS is becoming the technology of choice for
achieving cost-effective integration in wireless and wireline communication transceivers.
Several SiGe BiCMOS
technology nodes exist today at commercial foundries
ranging in complexity and performance from 0.35 to 0.18 µm
geometry and from 60 to 200 GHz Ft (Figure 1).
substrate capacitance by nearly a factor of 4 for a minimum
size NPN but can be removed to reduce wafer cost without
impacting other device parameters.
After formation of the CMOS wells, gate, and collector
sinker, a SiGe layer is deposited by use of a single wafer RTCVD reactor.
Figure 2: Self-aligned SiGe NPN transistor with deep trench. Self-aligned transistors have intrinsic and extrinsic base formed by a single patterning step leading to a narrow and well controlled link base and low base resistance.
.18 .15 .13 .1
Figure 1. SiGe BiCMOS nodes mapped across major end markets. Plotted as examples are Jazz’s SiGe60, SiGe90, SiGe120 and SiGe200 technologies.
In this paper, we will review advances in the performance of SiGe bipolar devices, the integration of these devices with
deep sub-micron CMOS, and advances in the realization of
high quality passive elements. In the final section of the
paper, we will review optimized SiGe BiCMOS technology
nodes and discuss performance of benchmark circuits.
High Performance SiGe Bipolar Transistors
Figure 2 shows a cross-section of a state of the art SiGe
bipolar transistor. The transistor is built by first forming the buried layer through an implant and subsequent epitaxial
growth. Shallow and deep trench isolation elements are then
built. Use of deep trench is an option that reduces collector-
Next, the emitter is formed. In state of the art technology, the emitter is self-aligned to the extrinsic base resulting in low extrinsic base resistance, high Fmax, and low noise figure.
Figure 3 shows the simulated dependence of base resistance
at peak Ft on base link width. In a self-aligned device, this dimension can be scaled aggressively ( 20V
0 .0 0 1
0 .0 0 0 0 1
0 .0 0 0 0 0 0 1
Figure 7. 2 fF/µm2 MIM capacitor constant stress lifetime. A lifetime of >1000 years is extrapolated for operation at 5V.
Table 1: Sample of optimized SiGe BiCMOS technology variants
3 um Top Metal
6 um Top Metal
S tre s s V o lta g e (V )
T op Metal
Figure 6. Inductor area as a function of inductance for a 4-turn inductor with peak Q of 10 built in 3 µm and 6 µm top metal respectively.
Capacitors also take up significant amount of die area and
focus has been toward increasing their density. 2 fF/µm2
capacitors are now being introduced into production. By
stacking 2 fF/µm2 capacitors higher capacitance density can be achieved. Figure 7 shows reliability data for a 2 fF/µm2 MIM capacitor which is capable of 5V operation and has a
breakdown voltage of >20V.
Technology nodes and...
Please join StudyMode to read the full document