Extended Arrays of Vertically Aligned Sub-10 nm Diameter  Si Nanowires by Metal-Assisted Chemical Etching Zhipeng Huang,† Xuanxiong Zhang,† Manfred Reiche,† Lifeng Liu,† Woo Lee,*,†,‡ Tomohiro Shimizu,† Stephan Senz,† and Ulrich Gosele*,† ¨ Max Planck Institute of Microstructure Physics, Weinberg 2, D-06120 Halle Germany, and Korea Research Institute of Standards and Science, Yuseong, 305-340 Daejon, Korea Received July 31, 2008
2008 Vol. 8, No. 9 3046-3051
Large-area high density silicon nanowire (SiNW) arrays were fabricated by metal-assisted chemical etching of silicon, utilizing anodic aluminum oxide (AAO) as a patterning mask of a thin metallic ﬁlm on a Si (100) substrate. Both the diameter of the pores in the AAO mask and the thickness of the metal ﬁlm affected the diameter of SiNWs. The diameter of the SiNWs decreased with an increase of thickness of the metal ﬁlm. Large-area SiNWs with average diameters of 20 nm down to 8 nm and wire densities as high as 1010 wires/cm2 were accomplished. These SiNWs were single crystalline and vertically aligned to the (100) substrate. It was revealed by transmission electron microscopy that the SiNWs were of high crystalline quality and showed a smooth surface.
In recent years silicon nanowires (SiNWs) have attracted much attention1,2 due to their many unique properties and potential applications as building blocks for advanced electronic devices,3,4 biological sensors,5,6 and optoelectronic devices,7,8 as well as for renewable energy devices.9 As in many applications of nanostructured materials, it is important not only to synthesize SiNWs with a high degree of regularity and uniformity in terms of diameter and length, but also to accurately position them in arrays. Fabrication of spatially well-resolved two-dimensional (2D) periodic arrays of vertically aligned epitaxial SiNWs with controlled density is of utmost importance for many practical applications, such as in ﬁeld-effect transistors (FET).3,4 To date, considerable efforts have been devoted to fabricating vertically aligned SiNWs. As a bottom-up approach, the vapor-liquid-solid (VLS) growth method10 utilizing catalytic metal nanoparticles is known to be a general way of the epitaxial growth of SiNWs with some degree of controllability over diameter and wire density.11,12 However, tight control over the diameter and spacing of SiNWs is rather difﬁcult to achieve unless colloidal catalytic metal particles with a tight diameter distribution or electron beam lithography are used. Moreover, easy application of the technique is limited to a speciﬁc * Corresponding author. E-mail: firstname.lastname@example.org (W.L.) and email@example.com (U.G.). Fax: +49-345-5511-223. † Max Planck Institute of Microstructure Physics. ‡ Korea Research Institute of Standards and Science. 10.1021/nl802324y CCC: $40.75 Published on Web 08/13/2008 © 2008 American Chemical Society
crystallographic orientation (i.e., 〈111〉). Vertical epitaxial growth of SiNWs on Si (100) wafers, which are conventionally used in current CMOS technology, still remains a challenge due to the preferred growth directions of SiNWs to 〈111〉, 〈112〉, and 〈110〉 depending on the diameter.13 Guided epitaxial growth of  SiNWs on Si (100) has been recently demonstrated by utilizing anodic aluminum oxide (AAO) as a template.14,15 However, the approach requires a preannealing of AAO above 800 °C prior to seeding of catalytic gold nanoparticles and an ultrahigh vacuum (UHV) system for subsequent VLS growth of nanowires. In addition, this approach has presently not yet been shown to work for nanowire diameters below about 60 nm. As a top-down approach, metal-assisted wet-chemical etching of silicon substrates16-19 in combination with nanosphere lithography20 is considered as a promising solution to achieve precise positioning of aligned SiNWs as well as control of diameter, length, spacing, and density, avoiding high-cost and low-throughput...