Shift Register

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  • Topic: Shift register, Flip-flop, Bit
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Shift registers
1.0 Introduction
Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes the input of the next flip-flop. Most of the registers possess no characteristic internal sequence of states. All flip-flop is driven by a common clock, and all are set or reset simultaneously.

In these few lectures, the basic types of shift registers are studied, such as Serial In - Serial Out, Serial In - Parallel Out, Parallel In – Serial Out, Parallel In - Parallel Out, and bidirectional shift registers. A special form of counter - the shift register counter, is also introduced. Register:

?? A set of n flip-flops
?? Each flip-flop stores one bit
?? Two basic functions: data storage (Figure 1.2) and data
movement (Figure 1.1).
Shift Register:
?? A register that allows each of the flip-flops to pass the stored information to its adjacent neighbour
?? Figure 1.1 shows the basic data movement in shift registers. Counter:
?? A register that goes through a predetermined sequence of states

Figure 1.1: Basic data movement in shift registers [Floyd]

Storage Capacity:
The storage capacity of a register is the total number of bits (1 or 0) of digital data it can retain. Each stage (flip flop) in a shift register represents one bit of storage capacity. Therefore the number of stages in a register determines its storage capacity.

Figure 1.2: The flip-flop as a storage element.

2.0 Serial In - Serial Out Shift Registers
The serial in/serial out shift register accepts data serially – that is, one bit at a time on a single line. It produces the stored information on its output also in serial form.

2.1 Example: Basic four-bit shift register

Figure 2.1
A basic four-bit shift register can be constructed using four D flip-flops, as shown in Figure 2.1.
The operation of the circuit is as follows.
?? The register is first cleared, forcing all four outputs to zero.

?? The input data is then applied sequentially to the D input of the first flip-flop on the left (FF0).
?? During each clock pulse, one bit is transmitted from left to right. ?? Assume a data word to be 1001.
?? The least significant bit of the data has to be shifted through the register from FF0 to FF3.

In order to get the data out of the register, they must be shifted out serially. This can be done destructively or non-destructively. For destructive readout, the original data is lost and at the end of the read cycle, all flip-flops are reset to zero.

FF0
0

FF1
0

FF2
0

FF3
0

1001

The data is loaded to the register when the control line is HIGH (ie WRITE). The data can be shifted out of the register when the control line is LOW (ie READ).
Clear
1001

FF0
0

FF0
1

FF1
0

FF0
1

FF1
0

FF1
FF2
0
0
WRITE:
FF2
FF3
0
1
READ:
FF2
FF3
0
1

FF3
0

0000

1001

Figure 2.2 illustrates entry of the four bits 1010 into the register. Figure 2.3 shows the four bits (1010) being serially shifted out of the register and replaced by all zeros.

Figure 2.2: Four bits (1010) being entered serially into the register.

Figure 2.3: Four bits (1010) being serially shifted out of the register and replaced by all zeros

2.2 5-bit serial in/serial out shift registers
Figure 2.4 illustrates entry of the five bits 11010 into the register.

Figure 2.4

3.0 Serial In - Parallel Out Shift Registers
For this kind of register, data bits are entered serially in the same manner as discussed in the last section. The difference is the way in which the data bits are taken out of the register. Once the data are stored, each bit appears on its respective output line, and all bits are available simultaneously. A construction of a four-bit serial in - parallel out register is shown below.

In the table below, we can see how the four-bit binary number 1001 is shifted to the Q outputs...
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