Hardware Implementation of Viterbi Decoder for Wireless Applications Bhupendra Singh1, Sanjeev Agarwal2 and Tarun Varma3
Deptt. of Electronics and Communication Engineering, Amity School of Engineering and Technology, Noida, India Email: firstname.lastname@example.org 2,3 Malaviya National Institute of Technology, Jaipur, India Email: email@example.com, firstname.lastname@example.org controlled shift register is designed at the circuit level and integrated into the ACS module. A. Structure of Viterbi Decoder The four functional blocks of VD in term of implementation, including branch metric unit (BMU), add-compare-select unit (ACSU), feedback unit (FBU) and survivor memory unit (SMU).
Abstract—In 2G mobile terminals, the VD consumes approximately one third of the power consumption of a baseband mobile transceiver. Thus, in 3G mobile systems, it is essential to reduce the power consumption of the VD. In this report the register exchange (RE) method, adopting a pointer concept, is used to implement the survivor memory unit (SMU) of the VD. For the implementation part, hardware implementation of MLVD through Synopsys Design Compiler Synthesis is done. For synthesis UMC-180nm Library is used. Index Terms— Viterbi Decoder, SMU, ACSU, RE, MLVD I. INTRODUCTION The register exchange (RE) method, adopting a pointer concept, is used to implement the survivor memory unit (SMU) of the VD. The method entails assigning a pointer to each register or memory location. The contents of the pointer, which points to one register, is altered to point to a second register, instead of copying the contents of the first register to the second. When the pointer concept is applied to the RE's SMU implementation, there is no need to copy the contents of the SMU and rewrite them, but one row of memory is still needed for each state of the VD. Thus, the VDs in CDMA systems require only 256 rows of memory, hence reducing the VD's power consumption. Also, if the initial state of the convolutional encoder is known, the entire SMU is reduced to only one row. Because the decoded data is generated in the required order, even this row of memory is dispensable. The zero-memory architecture is called the MemoryLess Viterbi Decoder (MLVD), and reduce power consumption. Another problem of the VD, which is addressed in this report, is the Add Compare Select Unit (ACSU) which is composed of 128 butterfly ACS modules. The ACSU's high parallelism has been previously solved by using a bit serial implementation. The 8-bit First Input First Output (FIFO) register, needed for the storage of each path metric (PM), is at the heart of the single bit serial ACS butterfly module. A new, simply
Fig.1 Functional Block of VD The BMU calculates branch metric of each branch according to maximum likelihood of the received data. The ACSU makes the sum of branch and path metrics, then compares and selects the survivor path metric and the decision bit. The FBU stores the survivor path metric for ACSU to be used in the next cycle. The SMU produces the decoded data based on the decision bit and the survivor path metric. The SMU marked by boldfaced letters in Fig. 1 significantly influences latency, power and chip area in a VD. B. Viterbi Decoding Algorithms In 1967, Viterbi developed the Viterbi Algorithm (VA) as a method to decode convolutional codes . The VA uses the trellis diagram to decode an input sequence, as demonstrated in Figure 2. The VA, which uses a hard decision format, is exhibited in Fig.2. A node is assigned to each state for each time stage.The transition between two states is represented by a branch, which is assigned a weight, referred to as a branch metric (BM). The BM is a measure of the likelihood of the transition, given the noisy observations. The BMs that are accumulated along a path form a path metric (PM). For the two...