Priority Interrupt

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  • Topic: Interrupt, Interrupts, Interrupt request
  • Pages : 6 (2015 words )
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  • Published : April 10, 2013
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Priority Interrupt 
. Priority interrupt is one of the methods of data transfer from CPU to peripheral devices Data is transferred from CPU to I/O devices on the initiation of CPU. But, the CPU cannot start the transfer unless the device is completely ready for communication with the CPU. The readiness of the device is checked only by the interrupt given by the device. The CPU responds to the request by storing the returned address from PC into the memory stack. Then the next job is of program to service that request by transfer of data. In a typical system number of I/O devices are connected to the system. Each of the devices is equally capable of producing the interrupt to talk to CPU and transfers the data. The first task of the interrupt handler is to identify the source of the request and the time it originates. Sometime it also happens that the requests generated are simultaneous. In such cases system has to decide which one to be served first. Priority interrupt is a system which assigns priority to the various devices and arranges them in order to serve them in case of simultaneous requests. The system may also decide determine which conditions are permitted to interrupt the computer while another request is being serviced or in other words it is responsible for determining the interrupting scope of the device.  Accordingly we can easily judge which task need to be of higher priority. Tasks which can’t be delayed or interrupted while execution otherwise some serious consequences can happen are always prioritized higher. For example devices like magnetic tapes which have high transfer rate are prioritized higher then the devices with slow data transfer like keyboard. As simple as it can be, the computer will serve that request first who’spriority is higher then the other if there is any conflict between the request creations. Establishing the priority of the interrupt can be through software or hardware. A polling process is used to identify the highest priority source by means of software. In this method there is one common branch address for all interrupts. The programs that care about the interrupt begin from the branch address and poll the interrupt in sequence. The order in which they are tested determines the priority of each source in sequence. The highest priority is served first and then the count down starts.  

The major disadvantage of this method is that if too many interrupts are generated and needed to be prioritized then the time required to prioritize them exceeds the time available for the service of I/O device. In hardware priority interrupt handler, there is one hardware unit that receives the interrupt from all the devices and then decides the priority without polling and is thus faster and efficient. INTERRUPTS

There are two main types of interrupt in the 8086 microprocessor, internal and external hardware interrupts. Hardware interrupts occur when a peripheral device asserts an interrupt input pin of the microprocessor.  Whereas internal interrupts are initiated by the state of the CPU (e.g. divide by zero error) or by an instruction.  Provided the interrupt is permitted, it will be acknowledged by the processor at the end of the current memory cycle. The processor then services the interrupt by branching to a special service routine written to handle that particular interrupt. Upon servicing the device, the processor is then instructed to continue with what is was doing previously by use of the "return from interrupt"   instruction. The status of the programme being executed must first be saved. The processors registers will be saved on the stack, or, at very least, the programme counter will be saved. Preserving those registers which are not saved will be the responsibility of the interrupt service routine. Once the programme counter has been saved, the processor will branch to the address of the service routine. Edge or Level sensitive Interrupts

Edge level interrupts are recognised on...
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