A New Area and Power Efficient Single Edge Triggered Flip-Flop Structure for Low Data Activity and High Frequency Applications Imran Ahmed Khan*, Mirza Tariq Beg Department of Electronics and Communication, Jamia Millia Islamia, New Delhi, India *Email address of Corresponding author: firstname.lastname@example.org Abstract In this work, a new area and power efficient single edge triggered flip-flop has been proposed. The proposed design is compared with six existing flip-flop designs. In the proposed design, the number of transistors is reduced to decrease the area. The number of clocked transistors of the devised flip-flop is also reduced to minimize the power consumption. As compared to the other state of the art single edge triggered flip-flop designs, the newly proposed design is the best energy efficient with the comparable power delay product (PDP) having an improvement of up to 61.53% in view of power consumption. The proposed flip-flop also has the lowest transistor count and the lowest area. The simulation results show that the proposed flip-flop is best suited for low power and low area systems especially for low data activity and high frequency applications. Keywords: PDP, reliability, delay, process node, clock frequency
The latest advances in mobile battery-powered devices such as the Personal Digital Assistant (PDA) and mobile phones have set new goals in digital VLSI design. The portable devices require high speed and low power consumption. So the power dissipation has become a prominent issue . For big circuits implementing complex functionalities like control units, microprocessors, usually a very large number of flip-flops are used. So the flip-flops heavily affect the performance of the entire system. This paper focuses on the minimization of power dissipation in the edge triggered flip-flops. Flip-flops are often used in computational circuits to operate in selected sequences during recurring clock intervals to receive and maintain data for a limited time period sufficient for other circuits within a system to further process data. The power, delay, and reliability of the flip-flops directly affect the performance and fault tolerance of the whole electronic system . Therefore, it is imperative to carefully design flip flops for minimum area, delay, power, and maximum reliability. Several flip-flop designs have been proposed for power reduction. Some of these designs require a large number of transistors for implementation, resulting in a large area, not necessarily suitable for small, low-priced systems. In this paper, a new high performance, low power and low transistor count single edge triggered flip-flop is devised. The proposed single edge triggered flip-flop is compared with the conventional designs. For all circuits, simulations are carried on 130nm process node using BSIM3 models. This paper is organized into five sections. Section 2 outlines the conventional flip flop structures investigated in this paper. In section 3, a new flip-flop
Innovative Systems Design and Engineering ISSN 2222-1727 (Paper) ISSN 2222-2871 (Online) Vol.4, No.1, 2013
is described. The nominal simulation conditions and results are discussed in section 4. Section 5 has concluding remarks.
CONVENTIONAL FLIP-FLOP STRUCTURES
To improve the performance of a conventional Transmission Gate Flip-Flop (TGFF shown in Fig. 1) [3, 4], addition of an inverter and transmission gate between the outputs of master and slave latches to accomplish a push–pull effect at the slave latch, was proposed in . The static Push Pull Flip-Flop (PPFF) is shown in Fig. 2. The semi-static Pass Flip-Flop (Pass FF) was proposed by  as shown in Fig. 3. The number of transistors of this flip-flop was reduced to decrease the power consumption. The four transistors in...