PIPELINED RADIX-2K FEED FORWARD FFT ARCHITECTURES
PIPELINED RADIX-2K FEED FORWARD FFT ARCHITECTURES
ABSTRACT
The Fast Fourier transform (FFT) is one of the most important algorithms in the field of digital signal processing. It is used to calculate the discrete Fourier transform (DFT) efficiently. In order to meet the high performance and real-time requirements of modern applications, hardware designers have always tried to implement efficient architectures for the computation of the FFT. In this context, pipelined hardware architectures are widely used, because they provide high throughputs and low latencies suitable for real time, as well as a reasonably low area and power consumption.
The appearance of radix- was a milestone in the design of pipelined FFT hardware architectures. Later, radix- was extended to radix- . However, radix- was only proposed for single-path delay feedback (SDF) architectures, but not for feed forward ones, also called multi-path delay commutator (MDC).
This paper presents the radix- feed forward (MDC) FFT architectures. In feed forward architectures radix- can be used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which make them suitable for the most demanding applications. Indeed, the proposed radix- feed forward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. As a result, the proposed radix- feed forward architectures not only offer an attractive solution for current applications, but also open up a new research line on feed forward structures.
In feed forward architectures radix- can be used for any number of parallel samples which is a power of two. Indeed, the number of parallel samples can be chosen arbitrarily depending of the
ABSTRACT
The Fast Fourier transform (FFT) is one of the most important algorithms in the field of digital signal processing. It is used to calculate the discrete Fourier transform (DFT) efficiently. In order to meet the high performance and real-time requirements of modern applications, hardware designers have always tried to implement efficient architectures for the computation of the FFT. In this context, pipelined hardware architectures are widely used, because they provide high throughputs and low latencies suitable for real time, as well as a reasonably low area and power consumption.
The appearance of radix- was a milestone in the design of pipelined FFT hardware architectures. Later, radix- was extended to radix- . However, radix- was only proposed for single-path delay feedback (SDF) architectures, but not for feed forward ones, also called multi-path delay commutator (MDC).
This paper presents the radix- feed forward (MDC) FFT architectures. In feed forward architectures radix- can be used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which make them suitable for the most demanding applications. Indeed, the proposed radix- feed forward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. As a result, the proposed radix- feed forward architectures not only offer an attractive solution for current applications, but also open up a new research line on feed forward structures.
In feed forward architectures radix- can be used for any number of parallel samples which is a power of two. Indeed, the number of parallel samples can be chosen arbitrarily depending of the