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  • Topic: MOSFET, Transistor, CMOS
  • Pages : 10 (2548 words )
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  • Published : January 8, 2013
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CMOS Fabrication Technology CMOS Fabrication Technology

Contents

1. Introduction 2. Fabrication Process Flow - Basic Steps 2.3. The CMOS n-Well Process 4. Advanced CMOS Fabrication Technologies Twin-Tub (Twin-Well) CMOS Process Silicon-on-Insulator (SOI) CMOS Process

Butterfly’s

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CMOS Fabrication Technology

CMOS Fabrication Technology

1. Introduction In the MOS chip fabrication, special emphasis needs to be laid on general outline of the process flow and on the interaction of various processing steps, which ultimately determine the device and the circuit performance characteristics. In order to establish links between the fabrication process, the circuit design process and the performance of the resulting chip, the circuit designers must have a working knowledge of chip fabrication to create effective designs and in order to optimize the circuits with respect to various manufacturing parameters. Also, the circuit designer must have a clear understanding of the roles of various masks used in the fabrication process, and how the masks are used to define various features of the devices on-chip. The following discussion will concentrate on the well-established CMOS fabrication technology, which requires that both n-channel (nMOS) and p-channel (pMOS) transistors be built on the same chip substrate. To accommodate both nMOS and pMOS devices, special regions must be created in which the semiconductor type is opposite to the substrate type. These regions are called wells or tubs. A p-well is created in an n-type substrate or, alternatively, an n- well is created in a p-type substrate. In the simple n-well CMOS fabrication technology presented, the nMOS transistor is created in the p-type substrate, and the pMOS transistor is created in the n-well, which is built-in into the p-type substrate. In the twin-tub CMOS technology, additional tubs of the same type as the substrate can also be created for device optimization.

Butterfly’s

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CMOS Fabrication Technology

Figure-1: Simplified process sequence for fabrication of the n-well CMOS integrated circuit with a single polysilicon layer, showing only major fabrication steps. The simplified process sequence for the fabrication of CMOS integrated circuits on a ptype silicon substrate is shown in Fig.1. The process starts with the creation of the n-well regions for pMOS transistors, by impurity implantation into the substrate. Then, a thick oxide is grown in the regions surrounding the nMOS and pMOS active regions. The thin gate oxide is subsequently grown on the surface through thermal oxidation. These steps are followed by the creation of n+ and p+ regions (source, drain and channel-stop implants) and by final metallization (creation of metal interconnects). 2. Fabrication Process Flow - Basic Steps Note that each processing step requires that certain areas are defined on chip by appropriate masks. Consequently, the integrated circuit may be viewed as a set of patterned layers of doped silicon, polysilicon, metal and insulating silicon dioxide. In general, a layer must be patterned before the next layer of material is applied on chip. The process used to transfer a pattern to a layer on the chip is called lithography. Since each layer has its own distinct patterning requirements, the lithographic sequence must be repeated for every layer, using a different mask.

Butterfly’s

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CMOS Fabrication Technology
To illustrate the fabrication steps involved in patterning silicon dioxide through optical lithography, let us first examine the process flow shown in Fig. 2. The sequence starts with the thermal oxidation of the silicon surface, by which an oxide layer of about 1 micrometer thickness, for example, is created on the substrate (Fig. 2(b)). The entire oxide surface is then covered with a layer of photoresist, which is essentially a light-sensitive, acidresistant organic polymer, initially insoluble in the developing solution (Fig....
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