Mips

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MIPS Architecture
 MIPS stands for 'Microprocessor without Interlocked

Pipeline Stages’  RISC Instruction Set Architecture  32 bit general purpose registers  PC (program counter) holds address of next instruction  all MIPS Instructions are same length  Few Instruction formats and simple addressing modes

Implementing MIPS
• • Implementation of the MIPS instruction set Simplified to contain only – arithmetic-logic instructions: add, sub, and, or, slt – memory-reference instructions: lw, sw – control-flow instructions: beq, j 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

op
6 bits

rs
5 bits

rt
5 bits

rd

shamt funct
16 bits

R-Format

op
6 bits

rs

rt
26 bits

offset

I-Format J-Format

op

address

MIPS Instruction Format
• An instruction like “add” consists of 6 fields
op
6

rs
5

rt
5

rd
5

shamt funct
5 6

 op: opcode

    

rs: first register source operand rt: second register source operand rd: register destination shamt: shift amount (see later) funct: function code (to select a variant of the operation, based on the opcode)

Overview: Processor Implementation Styles
• Single Cycle
– perform each instruction in 1 clock cycle – clock cycle must be long enough for slowest instruction; therefore, – disadvantage: only as fast as slowest instruction

• Multi-Cycle
– break fetch/execute cycle into multiple steps – perform 1 step in each clock cycle – advantage: each instruction uses only as many cycles as it needs

• Pipelined
– execute each instruction in multiple steps – perform 1 step / instruction in each clock cycle – process multiple instructions in parallel – assembly line

Implementing MIPS: the Fetch/Execute Cycle
• High-level abstract view of fetch/execute implementation – – – – – use the program counter (PC) to read instruction address fetch the instruction from memory and increment PC use fields of the instruction to select registers to read execute depending on the instruction repeat…

Data Register # Registers Register # Register # Data

PC

Address Instruction memory

Instruction

ALU

Address Data memory

5

Data path for MIPS
Stage 5

PC

Instruction Memory (Imem)

Registers

ALU

Data Memory (Dmem)

Stage 1


Stage 2

Stage 3

Stage 4

Use datapath figure to represent stages IFtch Dcd Exec Mem WB

ALU

IM

Reg

DM

Reg

MIPS Instruction Execution sequence
 Fetch instruction from memory  Read registers while decoding the instruction, the format of MIPS instructions allows reading and decoding to occur simultaneously  Execute the operation or calculate an address  Access an operand in data memory  Write the result into a register

Functional Elements
• Two types of functional elements in the hardware:
– elements that operate on data (called combinational elements) – elements that contain data (called state or sequential elements)

8

Combinational Elements
• • Works as an input  output function, e.g., ALU Combinational logic reads input data from one register and writes output data to another, or same, register – read/write happens in a single cycle – combinational element cannot store data from one cycle to a future one

Combinational logic hardware units
State element

State element 1

Combinational logic

State element 2

Combinational logic

Clock cycle

9

State Elements
• • • • • State elements contain data in internal storage, e.g., registers and memory All state elements together define the state of the machine – What does this mean? Think of shutting down and starting up again…

Flipflops are 1-bit state elements, equivalently, they are 1-bit memories The output(s) of a flipflop always depends on the bit value stored, i.e., its state, and can be called 1/0 or high/low or true/false The input to a flipflop can change its state depending on whether it is clocked or not…

10

State Elements on the Datapath: Register...
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