ECO Timing Optimization Using Spare Cells
and Technology Remapping
Kuan-Hsien Ho, Yen-Pin Chen, Jia-Wei Fang, Student Member, IEEE, and Yao-Wen Chang, Member, IEEE
Abstract —We introduce in this paper a new problem of
post-mask engineering change order (ECO) timing optimization using spare-cell rewiring and present a two-phase framework
for this problem. Spare-cell rewiring is a popular technique for incremental timing optimization and/or functional change after the placement stage. The spare-cell rewiring problem is very challenging because of its dynamic wiring cost nature
for selecting a spare cell, while the existing related problems consider only static wiring cost: once a standard cell is placed, its physical location is ﬁxed and so is its wiring cost. For the sparecell rewiring problem, each rewiring could make some spare cells become ordinary standard cells and some standard cells become new spare cells simultaneously. As a result, the wiring cost becomes dynamic and further complicates the optimization process. For the addressed problem, we present a two-phase
framework of 1) buffer insertion and gate sizing followed by 2) technology remapping. For Phase 1, we present a dynamic
programming algorithm considering the dynamic cost, called
dynamic cost programming, for the ECO timing optimization
with spare cells. Without loss of solution optimality, we further present an effective pruning method by selecting spare cells only inside an essential bounding polygon to reduce the solution space. For those ECO timing paths that cannot be ﬁxed during Phase 1, we apply technology remapping on the spare cells to restructure the circuit to ﬁx the timing violations. The whole framework is integrated into a commercial design ﬂow. Experimental results based on ﬁve industry benchmarks show that our method is very effective and efﬁcient in ﬁxing the timing violations of ECO paths. Index Terms—Engineering change order (ECO), gate sizing,
physical design, spare cells, technology remapping, timing optimization.
ITH THE DRAMATIC growth of circuit complexities
and the increasing pressure of time-to-market, more
Manuscript received June 17, 2009; revised October 14, 2009. Current version published April 21, 2010. This work was supported in part by ITRI, Springsoft, Synopsys, TSMC, and the National Science Council of Taiwan, under Grants NSC 98-2221-E-002-119-MY3, NSC 098-2811-E-002-138, NSC 97-2221-E-002-237-MY3, NSC 96-2628-E-002-249-MY3, and NSC 96-2628E-002-248-MY3, respectively. An earlier version of this paper was presented at the 2007 IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Jose, CA, November 2007 . This paper was recommended by Associate Editor, L. Scheffer.
K.-H. Ho and J.-W. Fang are with the Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan (e-mail: email@example.com; firstname.lastname@example.org).
Y.-P. Chen is with Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu 300, Taiwan (e-mail: email@example.com).
Y.-W. Chang is with the Department of Electrical Engineering and the Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan (e-mail: firstname.lastname@example.org).
Color versions of one or more of the ﬁgures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identiﬁer 10.1109/TCAD.2010.2043573
and more bugs are found in late design cycles. As a result,
engineering change order (ECO) is widely used to incrementally repair design bugs and thus can reduce the need for backtracking to earlier design stages for design correction. ECO can happen at different design stages, e.g., pre-layout, post-layout, post-mask, and even post-silicon stages. Different design stages suffer from different optimization limitations and...