Merging of Cmos with Nanotechnology

Topics: CMOS, Logic gate, Transistor Pages: 7 (1483 words) Published: January 16, 2011
EMTM 640

Dynamics of Semiconductor Industries

Paper 3:

Merging of CMOS with Nanotechnology – Hybrid Integration


Nishit Sahay



One of the key reasons behind the phenomenal success of Semiconductor industry is the scale down of transistors. Despite all the advancements in the CMOS technology, it has almost reached the level of saturation. The only breakthrough that would allow to make 1-nm-scale electron devices practical, would be the introduction of “CMOL” hybrid integrated circuits that would feature, in addition to an advanced CMOS substrate system, a layer of ultra-dense molecular electronic devices. A combination of CMOS technology and Nanotechnology is the CMOS-Nano hybrid technology, which can significantly enhance the scope of integrated circuits. Such CMOS-Nano hybrid systems try to utilize the advantages of both traditional CMOS systems and novel nanowire/ nanotube materials. This will enhance the IC performance in the near future and create a breakthrough in the long run. This paper introduces such ultra small electron devices.


CMOL is a suggested architecture which will help achieve scaling down below 10-nm. CMOL hybrid circuits are combination of CMOS components and molecular devices, interconnected by nanowires.

{Refer Exhibit 1} In this architecture, CMOS forms the lower level and the molecular devices will be at the top level. The transistor density of the CMOS layer will be relatively low, of the order of 108 CM2. This could be achieved by the new 45-nm-node technology. Vertical plugs will connect CMOS to the I/O pins, CMOS wiring, and the next level which is the nanowiring. The CMOS wires will need to be extremely narrow in order to sustain the required density of molecular devices.

Nanowire layers will be connected by self-assembling molecular devices with possibility of high density. With a 3-nm nanowire, the density of the active molecular component would be more than 3x1012 functions per cm2.

This will allow an optimal combination of strengths of its components. Robust universal CMOS circuits will take care of functions requiring high reliability, high voltage gain and high ON currents, in particular signaling over long distances as well as I/O functions. Molecular component will take care of functions requiring highest integration scale. The self assembly of molecular devices will keep the fabrication cost low and comparable to current fabrication cost of CMOS devices.


Exhibit 2 shows the topology which is the most widely used design for the research. Similar nanodevices are formed at each crosspoint of a nanowire crossbar. In this design , alignment between two nanowire level is not required. The crossbar needs to be interfaced with the CMOS subsystem. This will allow individual access to each crosspoint nanodevice. The silicon – nanowire interface is provided by sharp-tip, conical vias distributed all over the circuit area.

CMOL Components

A. Nanowire Crossbars

The biggest advantage of the hybrid CMOS/nanodevices is that it does not require the nanoscale layer alignment by lithography. Presently there are three basic options for the formation of crossbar nanowires: nanoimprint lithography, EUV interference lithography and block-copolymer lithography.

The block-copolymer lithography is most ready for applications. Some results have indicated that this technology may be scalable down to 8 – 10nm. The EUV interference lithography does not use masks and may be more suitable for going beyond 10-nm frontier.

B. Crosspoint Devices:

The crosspoint devices developed so far is assumed to have programmable diodes functionality. At low applied voltage, such devices work as diode. This functionality can be leverage to develop memory cells storing 1 bit information in its internal state.


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