A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a computer hardware component responsible for handling accesses to memory requested by the central processing unit (CPU). Its functions include translation of virtual addresses to physical addresses (i.e., virtual memory management) memory protection,cache control, bus arbitration, and, in simpler computer architectures (especially 8-bit systems), bank switching. How it works
Modern MMUs typically divide the virtual address space into pages, each having a size which is a power of 2, usually a few kilobytes. The bottom n bits of the address are left unchanged. The upper address bits are the (virtual) page number. The MMU normally translates virtual page numbers to physical page numbers via an associative cache called a Translation Look aside Buffer (TLB). When the TLB lacks a translation, a slower mechanism involving hardware-specific data structures or software assistance is used. The data found in such data structures are typically called page table entries (PTEs), and the data structure itself is typically called a page table. The physical page number is combined with the page offset to give the complete physical address. Examples
VAX pages are 512 bytes, which is very small. An OS may treat multiple pages as if they were a single larger page, for example Linux on VAX groups 8 pages together, so that the system is viewed as having 4 KiB pages. The VAX divides memory into 4 fixed-purpose regions, each 1 GiB in size. x86
The x86 architecture has evolved over a long time while maintaining full software compatibility even for OS code. Thus the MMU is extremely complex, with many different possible operating modes. DEC Alpha
The DEC Alpha processor divides memory into 8192-byte pages. After a TLB miss, low-level firmware machine code (here called PAL code) walks a 3-level tree-structured page table. Addresses are broken down as follows:...