With designs becoming increasingly complex by the day and transistor geometries shrinking, almost all the functional domains across SoC design teams are having a hard time to signoff their functions and Static Timing Analysis (STA) timing closure is also no exception. STA Timing closure is always an important and critical part of SoC design and lower technology nodes have only compounded the challenges for STA teams. As the VLSI industry has entered the epoch of a lower technology node, diminishing transistor sizes and interconnect lengths have disturbed the ratio of cell and interconnect delays. This leads to requirement of signing off the SoC at multiple corners. After timing signoff at multiple Processes, Voltage, Temperature (PVT) corners, the silicon fabricated at submicron technology nodes shows appreciable increase in yield in terms of meeting timing specifications of the design. However, timing closure at multiple PVT corners is in itself a huge challenge for the physical design team. This article will discuss these challenges and touch upon methodologies available to overcome them. We will discuss in detail, our solution to reduce the number of optimization corners in order to achieve efficient and coherent timing closure in minimum time. But before this, let us discuss in brief, the need to have multiple PVT corners for timing signoff. Cell delays and interconnect delays are governed by manufacturing Process (P), operating Voltage (V) and ambient Temperature (T) properties of dies. These factors determine the physical properties of cells and interconnect like W/L ratio of cells and Resistance (R) and Capacitance (C) value of interconnects. At the 180-nm technology node and above, timing signoff at worst and best standard cell PVT corners with 2 RC extraction corners, namely, Cmax Rmin (Cmax) , and Cmin Rmax ( Cmin) was sufficient. On similar lines at 90 nm node 2 additional process corners Best Hot (Best process, Voltage at max temperature) and Worst cold (Worst process, voltage at min temperature) were introduced for the robust timing signoff, specifically for hold timing signoff as hold is skew dependent . The RC corners for these 2 process corners were similarly Cmax at min temperature and Cmin at max temperature respectively. In 90-nm technology and above, a timing path is predominantly governed by cell delays. However below 90nm node, the contribution of interconnect delay in a timing path is significant and the Coupling Cap component (Cc) in net delay can significantly alter slack values at an endpoint of a timing path. The RC corners have to be split up wherein the contribution of each component Ground Capacitance (Cg) and Coupling Capacitance (Cc) has to be accounted separately. So on top of the 2 conventional RC corners Cmax and Cmin we have 2 more foundry specified RC corners: * XTALK ( Cc is max , Cg is min , R is min)
* Delay (Cc is min ,Cg is maximum, R is max)
Another important thing to note here is that interconnects and logical cells on single die can have different process. (For e.g., Interconnects manufactured with worst process and logical cells with best process and vice-versa). The possible cell corners and RC corners are shown in tables below.
S,o to summarize, working at technology nodes below 90-nm requires timing signoff at 4 PVT cell corners (Worst hot, worst cold, Best hot and Best cold) and 4 RC extraction corners (Cmax, Cmin,Xtalk and Delay). In all we have 4 X 4 = 16 corners for a single Timing Mode/View. If we have 8 STA modes for a design, then in all we have 8 X16 = 128 runs for the design. The first solution to avoid such an enervating analysis for a single mode is to look for a corner that forms a superset of the reset of corners. However a graphical distribution of slack values for a design block across all the 16 corners shows that none of the 16 corners was a complete superset over the others, thereby leaving us with no other...