# Mca Ignou

Topics: Central processing unit, Processor register, Computer architecture Pages: 23 (7501 words) Published: July 7, 2011
Course Code Course Title Assignment Number Maximum Marks Weightage Last Dates for Submission

: : : : : :

MCS-012 Computer Organisation and Assembly Language Programming MCA(1)/012/Assign/2011 100 25% 15th April, 2011 (For January Session) 15th October, 2011 (For July Session)

There are four questions in this assignment, which carries 80 marks. Rest 20 marks are for viva voce. You may use illustrations and diagrams to enhance the explanations. Please go through the guidelines regarding assignments given in the Programme Guide for the format of presentation. Answer to each part of the question should be confined to about 300 words. Question 1: (a) Perform the following arithmetic operations using binary signed 2’s complement notation for integers. You may assume that the maximum size of integers is of 10 bits including the sign bit. (Please note that the numbers given here are in decimal notation) (3 Marks) i) Ans: Add – 498 and 260

ii) Ans:

Subtract 456 from – 56

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iii) Ans:

(b) Convert the hexadecimal number: FA BB C9 into binary, octal and decimal. Ans1: (FA BB C9)16 = (0110011001001011000111)2 Ans2: (FA BB C9)16 = (77735711)8 Ans3: (FA BB C9)16 = (16759753)10

(1 Mark)

(c) Convert the following string into equivalent ASCII code – “Copyright © 2001 - 2011”. Include ASCII code of spaces between words in the resultant ASCII. Are these codes same as that used in Unicode? (2 Marks) Ans: 43h6fh70h79h72h69h67h68h74h20h28h43h29h20h32h30h30h30h20h32h

30h31h31h Character C o p y r i g h t space ( c ) space 2 0 0 0 space ASCII 43H 6FH 70H 79H 72H 69H 67H 68H 74H 20H 28H 43H 29H 20H 32H 30H 30H 30H 20H UNICODE 0043 006F 0070 0079 0072 0069 0067 0068 0074 0020 0028 0043 0029 0020 0032 0030 0030 0030 0020

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2 0 1 1

32H 30H 31H 31H

0032 0030 0031 0031

Yes the codes are same in ASCII & UNICODE

(d) Design a logic circuit that accepts a four digit binary input and creates an odd parity bit, a sign check bit and a more than two zero value test bit. The odd parity bit is created for the four bit data. The sign bit is set to 1 if the left most bit of the data is 1. Zero value bit is set to 1 if three of the input bits are zero. Draw the truth table and use K-map to design the Boolean expressions for each of the output bits. Draw the resulting circuit diagram using AND – OR – NOT gates. (5 Marks) Ans:

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(e ) A sequential circuit has two D flip flops A and B, two inputs x and y and one output z. Flip flops input equations and the circuit output are as follows: (5 Marks) DA = x B’ DB = y A + x’ A’ z=A+B (i) Draw the circuit diagram for the above.

Clock

X

Y

CxB’ CyA’

D A A’

A

Z

Cx’A’ CyA+x’A’
D B B’

B

(ii) x 0 0 0 0 0 0 0 0 1 1

Tabulate the state table for the flip flops. Present State Next State y A B A B 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 Page 4

1 1 1 1 1 1

0 0 1 1 1 1

1 1 0 0 1 1

0 1 0 1 0 1

(f) Design a floating point representation of 32 bits closer to IEEE 754 format except that the exponent of the representation should be of 4 bits only. You may assume that the mantissa is in normalised form; the exponent bias of 7; and one bit is used for the sign bit. Represent the number (89.125) 10 using this format . (4 Marks) Ans:

Question 2: (a) A RAM has a capacity of 64 K × 64. (2 Marks) (i) Ans: How many data input and data output lines does this RAM need to have? 64, since the word size is 64.

(ii) Ans:

How many address lines will be needed for this RAM? 64K = 64 × 1024 = 65536 words. Hence, there are 65536 memory addresses. Since 65536 = 16

2 it requires 16 bits address code to specify one of 65536 addresses.

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(b) Consider a RAM of 256 words with a word size of 16 bits. Assume that this memory have a cache memory of 8 Blocks with block size of 32 bits. For the given memory and Cache in the statements as above, draw a diagram to show the address mapping of...