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  • Topic: Electronic design automation, Integrated circuit design
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  • Published : March 13, 2013
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Banlawe, Ivane Ann P.
David, Joana Haizan G.
Landicho, Lloyd Charles L.

Mapuá Institute of Technology
2012

LE Design Verification

Table of Contents

Table of Contents
Cover Page

i

Table of Contents

ii

I.

Introduction

1

II.

Running DRC (Design Rule Check)

2

III. Running LVS (Layout Versus Schematic)

5

IV. Running LPE (Layout Parasitic Extraction)

8

V. Reference

Compiled by: Banlawe, Ivane Ann P.
David, Joana Haizan G.
Landicho, Lloyd Charles L.

13

ii

LE Design Verification

Introduction

I. Introduction
DESIGN RULE CHECK (DRC)
Design Rule Checking or Check(s) (DRC) is the area of Electronic Design Automation that determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called Design Rules.

Some examples of DRC’s in IC design include:


Active to active spacing



Well to well spacing



Minimum channel length of the transistor



Minimum metal width



Metal to metal spacing

LAYOUT VERSUS SCHEMATIC (LVS)
The LVS (Layout versus Schematic) check performs LVS comparison to verify that the design layout accurately represents the electronic equivalent of the design schematic. Hercules LVS verifies whether the physical design matches the schematic by: extracting the devices, verifying the connectivity between the devices and comparing the extracted information with the schematic netlist. Notice that in order to pass LVS, schematic names and layout names must match one to one. Make sure the names for labels and pins are using uppercase letters instead of lowercase letters. Also transistor dimensions for gate width and length in layout and schematic must match.

LAYOUT PARASITIC EXTRACTION (LPE)
After passing DRC and LVS you can now move on to LPE (Layout Parasitic Extraction). In this phase, resistive and capacitive components will be extracted from the layout.

Compiled by: Banlawe, Ivane Ann P.
David, Joana Haizan G.
Landicho, Lloyd Charles L.

1

LE Design Verification

II.

Design Rule Check

Running DRC

In the Editor window, go to: Verification DRC  Setup and Run to invoke DRC setup window.

1. User Interface Window

In the Main Tab:
a. For the Run Directory, the default is the name of your cell. b. The layout format is OpenAccess, select the library, the cell, and the cellview. c. The Job Parameter tool is Hercules
i.
You can check Launch Debugger to launch Hercules debugger window. ii.
You can check View Output to launch text viewer which opens the .LAYOUT_ERRORS file. This file is located at your indicated Run Directory. d. The runset is reference_drc.ev from the directory LE_Labs/PDK/hercules/drc/

In the Custom Options Tab:
a. Layer map is reference90RF_layer.map, from the directory LE_Labs\PDK\techfiles. b. Click OK/Apply in the DRC Setup window

Compiled by: Banlawe, Ivane Ann P.
David, Joana Haizan G.
Landicho, Lloyd Charles L.

2

LE Design Verification

Design Rule Check

Click OK when this window appears to start DRC Checking.

2. Confirmation and Warnings
a. After DRC is done, the console will return the following message:

b. If the layout has no errors and meets all the design rules, the output file .LAYOUT_ERRORS will display CLEAN (as shown below). If there are errors, it will return ERROR and the error details are listed in the file. Go to your indicated Run Directory to locate the text file.

Compiled by: Banlawe, Ivane Ann P.
David, Joana Haizan G.
Landicho, Lloyd Charles L.

3

LE Design Verification

Design Rule Check

c. If the Launch Debugger is checked and there are no layout errors, the Hercules debugger window will return the following message:

You can also manually launch this window by going to: Verification  Debug. If there are errors, the window will say “ERROR”

Errors can easily be found in the DRC Errors tab. Just click on an error listed in the ErrorCheck then...
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