Logic Gates

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  • Topic: Logic gate, Addition, XOR gate
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September 18th, 2007 CSC343 Fall 2007 Prepared by: Steven Medina

The purpose of this lab is to show you how to implement an adder using Quartus. As the name implies, adders are used to add two sets of values together. Adders are a very common design in digital design. For example, a CPU will use an adder to have its program counter point to its next instruction. This is done by adding a constant value of 4 to the current instructions memory address. You will be using adders both here, and in future labs. You will be shown three different kinds of adders. They are the half-adder, the full-adder. And the ripple carry adder. The purpose is to show you not only what each is, but why they are important. You will learn why each is important as you go through this lab. After creating our adder designs in Quartus, you will test your design on Altera’s DE2 programmable board. The DE2 board will be explained later in this lab.

A half-adder (HA) is an adder that accepts two inputs and gives two outputs. The two inputs are the two single bit binary values that will be added to each other. The two outputs represent the sum. We need two outputs (rather than one output) because the sum may have a carry bit. For example, in binary, 1+0 = 1. This situation has no carry bit in the output. In other words, the output itself is 1 bit. However, if we add 1+1, we get 10. This output is 2 bits long. This is a case where the carry-bit for the output is needed. A half adder consists of two logic gates. These are an AND gate, and an Exclusive OR gate. A diagram of a half adder is shown below.

. Figure 1: Half Adder using XOR and AND gate.

For the design of the half adder, do the following. 1) Create a new project in Quartus. Where it asks for the family or device you wish to target for compilation, select the Cyclone II board. Under the list of available devices, click EP2C35F672C6. 2) Design the half-adder shown in figure 1 in a...
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