September 18th, 2007 CSC343 Fall 2007 Prepared by: Steven Medina

PURPOSE
The purpose of this lab is to show you how to implement an adder using Quartus. As the name implies, adders are used to add two sets of values together. Adders are a very common design in digital design. For example, a CPU will use an adder to have its program counter point to its next instruction. This is done by adding a constant value of 4 to the current instructions memory address. You will be using adders both here, and in future labs. You will be shown three different kinds of adders. They are the half-adder, the full-adder. And the ripple carry adder. The purpose is to show you not only what each is, but why they are important. You will learn why each is important as you go through this lab. After creating our adder designs in Quartus, you will test your design on Altera’s DE2 programmable board. The DE2 board will be explained later in this lab.

HALF-ADDER
A half-adder (HA) is an adder that accepts two inputs and gives two outputs. The two inputs are the two single bit binary values that will be added to each other. The two outputs represent the sum. We need two outputs (rather than one output) because the sum may have a carry bit. For example, in binary, 1+0 = 1. This situation has no carry bit in the output. In other words, the output itself is 1 bit. However, if we add 1+1, we get 10. This output is 2 bits long. This is a case where the carry-bit for the output is needed. A half adder consists of two logic gates. These are an AND gate, and an Exclusive OR gate. A diagram of a half adder is shown below.

. Figure 1: Half Adder using XOR and AND gate.

For the design of the half adder, do the following. 1) Create a new project in Quartus. Where it asks for the family or device you wish to target for compilation, select the Cyclone II board. Under the list of available devices, click EP2C35F672C6. 2) Design the half-adder shown in figure 1 in a...

...Lab 1: Digital Logic Lab Introduction
Date of experiment: 1/30/2014
Date of Submission: 6/2/2014
Submitted by: Evgeniya Koshelyaevskaya
Group partners : Constantin Bercov, Rachel Revzin
College of Staten Island
Objective
1. To get familiar with the Cadet station and the basic equipment used for the experiment.
2. To investigate the behavior of the IC Chips obtained from the technician.
3. Compare theoretical data with the obtained...

...EXPT NO. :1 STUDY OF LOGICGATES
DATE :
AIM:
To study about logicgates and verify their truth tables.
APPARATUS REQUIRED:
SL No. | COMPONENT | SPECIFICATION | QTY |
1. | AND GATE | IC 7408 | 1 |
2. | OR GATE | IC 7432 | 1 |
3. | NOT GATE | IC 7404 | 1 |
4. | NAND GATE 2 I/P | IC 7400 | 1 |
5. | NOR GATE | IC 7402 | 1 |
6. | X-OR...

...and 0 at a regular rate over time. Due to the fact that the system can only store a finite number of states, sequential systems are sometimes called finite state machines (FSMs). A sequential system consists a set of memory devices and combination logic. Here, we focus on sequential systems with latches and flip flops.
Definitions of Terms
State: This is what is stored in the memory. It’s stored in binary devices but is not always naturally binary.
State Table: Shows...

...functional logic based mobile robot that can traverse and follow the black line track as accurate and as fast as possible.
2. To be able to understand the basic concepts behind different sensor technologies and apply it to the line detecting circuit of the line following mobile robot.
3. To be able to establish the relationship between the electrical and mechanical components of the line following mobile robot.
4. To be able to see a functional real time application of...

...B.E. PROJECT ON X-MASKING TECHNIQUES AND TEST DATA COMPACTION FOR LOGIC BUILT-IN SELF TEST
A DISSERTATION SUBMITTED TOWARDS THE PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE AWARD OF A DEGREE IN BACHELOR OF ENGINEERING IN ELECTRONICS AND COMMUNICATION Submitted By
HIMANSHU DOVAL VARUN KAPOOR (2K7/EC/643) (2K7/EC/713)
UNDER THE GUIDANCE OF
DR. ASOK BHATTACHARYYA
DEPARTMENT OF ELECTRONICS AND COMMUNICATION DELHI COLLEGE OF ENGINEERING 2011
ABSTRACT
Testing is...

...Logic Effort-
The method of logical effort is a term coined by Ivan Sutherland and Bob Sproull in 1991, is a straightforward technique used to estimate delay in a CMOS circuit. Used properly, it can aid in selection of gates for a given function (including the number of stages necessary) and sizing gates to achieve the minimum delay possible for a circuit.
Each logicgate is characterized by two quantities: its logical...

...Activity 6.3.2 LogicGates Introduction A two-valued number system is the basis for all of the powerful computers and electronic devices in the world. Those two values are 0 and 1. Everything in the digital world is based on this binary system. While it seems very simple, the binary system is used to create the logic that dictates the actions of complex and simpler digital systems. But how do processors know what to do with all of those 0s and 1s...

...from the 2nd edition
of the book Fundamentals of Digital Logic with VHDL Design. Since not all of these examples
are relevant to ECE241, the numbering of examples, and some ﬁgure numbers, are not always
sequential in this document.
Example 3.9
Problem: We introduced standard cell technology in section 3.7. In this technology, circuits are
built by interconnecting building-block cells that implement simple functions, like basic logicgates.
A...