The method of logical effort is a term coined by Ivan Sutherland and Bob Sproull in 1991, is a straightforward technique used to estimate delay in a CMOS circuit. Used properly, it can aid in selection of gates for a given function (including the number of stages necessary) and sizing gates to achieve the minimum delay possible for a circuit. Each logic gate is characterized by two quantities: its logical effort and its parasitic delay. These parameters may be determined in three ways: _ Using a few process parameters, one can estimate logical effort and parasitic delay as described in this chapter. The results are sufficiently accurate for most design work.
_ Using test circuit simulations, the logical effort and parasitic delay can be simulated for various logic gates. This technique is explained in Chapter 5. _ Using fabricated test structures, logical effort and parasitic delay can be physically measured.
Logical effort captures enough information about a logic gate’s topology—the network of transistors that connect the gate’s output to the power supply and to ground—to determine the delay of the logic gate. In this section, we give three equivalent concrete definitions of logical effort. Definition 4.1 The logical effort of a logic gate is defined as the number of times worse it is at delivering output current than would be an inverter with identical input capacitance.
Any topology required to perform logic makes a logic gate less able to deliver output current than an inverter with identical input capacitance. For one thing, a logic gate must have more transistors than an inverter, and so to maintain equal input capacitance, its transistors must be narrower on average and thus less able to conduct current than those of an inverter with identical input capacitance. If its topology requires transistors in parallel, a conservative estimate of its performance will assume that not all of them conduct at once, and therefore that they will not deliver as much current as could an inverter with identical input capacitance. If its topology requires transistors in series, it cannot possibly deliver as much current as could an inverter with identical input capacitance. Whatever the topology of a simple logic gate, its ability to deliver output current must be worse than an inverter with identical input capacitance. Logical effort is a measure of how much worse.
Definition 4.2 The logical effort of a logic gate is defined as the ratio of its input capacitance to that of an inverter that delivers equal output current. This alternative definition is useful for computing the logical effort of a particular topology. To compute the logical effort of a logic gate, pick transistor sizes for it that make it as good at delivering output current as a standard inverter, and then tally up the input capacitance of each input signal. The ratio of this input capacitance to that of the standard inverter is the logical effort of that input to the logic gate. The logical effort of a logic gate will depend slightly on the mobilitiy ratio in the fabrication process used to build it. These calculations are shown in detail later in this chapter.
Definition 4.3 The logical effort of a logic gate is defined as the slope of the gate’s delay vs. fanout curve divided by the slope of an inverter’s delay vs. fanout curve.
This alternative definition suggests an easy way to measure the logical effort of any particular logic gate by experiements with real or simulated circuits of various fanouts.
4.2 Grouping input signals
Because logical effort relates the input capacitance to the output drive current available, a natural question arises: for a logic gate with multiple inputs, how many of the input signals should we consider when computing logical effort? It is useful to define several kinds of logical effort, depending on how input signals are grouped. In each case, we define an input group to contain the input signals that are...
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