# Lab Manual

Topics: Circuit diagram, Electronic design automation, VHDL Pages: 22 (2801 words) Published: October 30, 2012
LABORATORY MANUAL

CE/CZ1005 : Digital Logic
CPE/CSC104 : Logic Design
[Location: Digital Systems Laboratory, N4-B1a-05]

Experiment 3 :
Combinational Logic Design
with Schematics and Structural
Verilog

Semester 1 2012/2013

COMPUTER ENGINEERING COURSE
COMPUTER SCIENCE COURSE

SCHOOL OF COMPUTER ENGINEERING
NANYANG TECHNOLOGICAL UNIVERSITY

CE/CZ1005/CPE/CSC104 Digital Logic

Experiment 3

COMBINATIONAL LOGIC DESIGN WITH SCHEMATICS
AND STRUCTURAL VERILOG

1.

OBJECTIVES

1.1

To further explore logic circuit design with the Xilinx FPGA design tool chain.

1.2

To design one segment of a 7-segment decoder using schematic capture.

1.3

To design a 7-segment decoder with structural Verilog statements.

1.4

To selectively display a digit using a push button.

2.

LABORATORY
This experiment is conducted at Digital Systems Laboratory, N4-B1a-05.

3.

EQUIPMENT AND SOFTWARE
Personal computer
Xilinx FPGA tool chain (ISE, ISIM, iMPACT)
Xilinx University Programme (XUP) Spartan 6 ATLYS development board Digilent PmodSSD Peripheral Module Board (7-segment display)

Sem 1 2012/2013

Page 1

CE/CZ1005/CPE/CSC104 Digital Logic

Experiment 3

4.

INTRODUCTION

4.1

In Experiment 2, you have designed and tested a 2’s complement adder/subtractor circuit on the Xilinx FPGA. In this experiment, you will go through a similar design process to implement the logic circuit of a 7-segment decoder.

Figure 1 shows the diagram of a 7-segment decoder and display. The segments are labeled a, b, c, d, e, f and g. By lighting up the correct segments (e.g. a, b and c in Figure 1), different numeric digits (e.g. “7” in Figure 1) can be displayed. Table 1 lists the hexadecimal digits that can be displayed.

X[3:0]

7-segment
display
decoder

Seg[6:0]

Figure 1: 7-segment decoder and display (e.g. displaying the digit “7”)

Table 1: Truth table of a 7-segment display decoder
Inputs X[3:0]
digits (binary)
0 (0000)
1 (0001)
2 (0010)
3 (0011)
4 (0100)
5 (0101)
6 (0110)
7 (0111)
8 (1000)
9 (1001)
A (1010)
B (1011)
C (1100)
D (1101)
E (1110)
F (1111)

4.2

a
1
0
1
1
0
1
1
1
1
1
1
0
1
0
1
1

b
1
1

Outputs
Segments (1: on, 0: off)
c
d
e
1
1
1
1
0
0

f
1
0

g
0
0

1
1
1

1
1
1

0
1
1

0
1
0

0
1
1

0
1
1

0
0

1
0

1
1

1
1

1
1

1
0

Fill in the remaining values in Table 1. Draw a Karnaugh map for each of the 7 outputs: a, b, c, d, …, and g; obtain the minimized Sum-of-Product (SOP) expression for each output.

Sem 1 2012/2013

Page 2

CE/CZ1005/CPE/CSC104 Digital Logic

Experiment 3

For example, the minimized SOP expression for a is:
a = X3’X2X0 + X2X1 + X3’X1 + X3X0’ + X3X2’X1’
+ X2’X0’
where X3, X2, X1, X0 are the 4 bits
of the hexadecimal digit (X3 is msb)

Kmap for
a
00
X3,X2

01
11
10

00
1
0
1
1

X1,X0
01 11
0
1
1
0
1

1
1
0

10
1
1
1
1

4.3

Obtain the minimized SOP expressions for each of the remaining segments: b to g. You will need to obtain these expressions before the experiment.

4.4

Sketch the logic circuit diagram of segment e using AND, OR and NOT gates before you implement it using the Xilinx schematic editor. You should only need four 2-input AND, one 4input OR and two NOT gates.

4.5

Following similar procedures in experiment 2, you will implement the segment, generate the program file and download it to the FPGA board for testing.

4.6

In this experiment, you will also design the 7-segment decoder using simple structural Verilog HDL statements to describe logic expressions. The essential information on structural Verilog is included in the Appendix.

Sem 1 2012/2013

Page 3

CE/CZ1005/CPE/CSC104 Digital Logic

Experiment 3

5.

EXPERIMENT

5.1

SET UP DESIGN ENVIRONMENT
The steps are essentially the same as those in Experiment 2. You may view the...