Intel Itanium Arcgitecture

Topics: X86, X86-64, Itanium Pages: 14 (3685 words) Published: February 27, 2013



Intel Itanium Architecture
Intel Itanium Architecture or IA-64: Intel and Hewlett-Packard developed the Itanium processor jointly. The Itanium is also called IA-64 (Intel Architecture 64 bit processor) uses 64-bit registers and performs 64-bit arithmetic and logic operations (figure 1). The Itanium architecture also provides full compatibility with Intel's 32-bit architecture also known as IA-32. [pic]

Figure1: 64-bit registers in an Itanium chipset.
The working operations of various registers that are used in an Itanium chipset are as follows: 1. Integer Register:128 64-bit+1bit NaT general registers and are shown by GR0 to GR127. GR0 is hardwired to zero, thus the content of it is set to zero. Figure 2 shows general register with an extra bit called Not a Thing (NaT) Figure 2:

Figure 2: General register with an extra bit called Not a Thing (NaT). 2. Floating Point Register: 128 82-bit floating point registers represented by FR0 through FR127, where FR0 and FR1 are set to zero and 1 respectively.  3. Qualify Predicate Register: 64 1-bit predicate register represented by P0, P1, P2, P3… P63, where P0 is set to zero. When the value of Pi is true (=1), the instruction using Pi is executed and when value of Pi for an instruction is false (0), the instruction act as NOP. 4. Branch Register: 8 64-bit Branch Registers are represented by br0 through br7. 5. Loop Count (LC) Register:  The Loop Count (LC) register is a 64-bit counter that is used for counting loops.     6. Current Frame Maker (CFM) Register: CMF register is a 38-bit register and is used to represent register stack. 7. Instruction Pointer (IP): The 64-bit instruction pointer holds the address of the bundle of the currently executing instruction. Each bundle consists of three instructions and a 5-bit template. The IP cannot be directly read or written thus it is incremented as instructions are executed. Each time IP is incremented by 16 because each instruction bundle requires 16 bytes. 8. Control and Status Registers:

a)     Application Registers: 128 64-bit application registers are represented by Ar0 through Ar127.  Some of the application registers are used for compatibility with IA-32 architecture. b)     User Mask (UM) Register: UM is 6-bit register and is used for defining data operation types such as big endian, little endian, and enabling or disabling performance monitor. c)     CPU Identification Registers: There are 5 64-bit registers that are called processor identification register or CPUID. These registers hold information about CPU such as processor ID, processor revision numbers, processor family number, and processor architecture revision number. Performance monitors: PMC and PMD

Intel Itanium Instructions: In general Itanium instructions have the following formats: [(qp)] mnemonic [.comp1[.comp2]  Dest= Srces, where parameters in bracket  are optional such as (qp), comp1 and comp2. (qp): qp is called qualify predicate bit  and it refers to any bit in the predicate register (.comp1) and (.comp2) are called completers and are used to set predicate bits of the predicate register. Some instructions may not have any completer, and some may have only one or two completers. Mnemonic is used to identify operation’s type such as ADD for addition, SUB for subtraction and COM for compare. Dest is the destination.

Srces are source operands and can be one or more sources depending on the instruction. Integer Instructions:
1.     Add Instruction: Register operation is as follows.   a)     add r1 = r2, r3  thus 1= r2+r3 ; r2 is the first operand and r3 is the second operand. b)     Add with  Predicate bit:
(p1) add r1 = r2, r3 thus if predicate bit p1 equal to 1 the instruction will execute, if p1=0  the instruction will not execute
add r1 =...
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