• Accessing I/O Devices • I/O interface • Input/output mechanism Memory-mapped I/O y pp / Programmed I/O Interrupts Direct Memory Access
Synchronous Bus Asynchronous Bus
I/O in CO and O/S
• • • Programmed I/O Interrupts DMA (Direct memory Access)
A bus is a shared communication link, which uses one , set of wires to connect multiple subsystems. The two major advantages of the bus organization are versatility and low cost.
Accessing I/O Devices
• Most modern computers use single bus arrangement for connecting I/O devices to CPU & Memory • The bus enables all the devices connected to it to exchange information • Bus consists of 3 set of lines : Address, Data, Control • Processor places a particular address (unique for an I/O Dev.) on address lines • Device which recognizes this address responds to the commands issued on the Control lines • Processor requests for either Read / Write • The data will be placed on Data lines
Hardware to connect I/O devices to b t bus
• Interface Circuit – Address Decoder – Control Circuits – Data registers – Status registers
• The Registers in I/O Interface – buffer and control • Flags in Status Registers like SIN, SOUT Registers, SIN • Data Registers, like Data-IN, Data-OUT
I/O interface for an input device
Address Add Decoders
Control C t l circuits
Data d t t D t and status registers
I/O /O Interface
Input device (s) p ( )
Input Output mechanism h i
• Memory mapped I/O • Programmed I/O • Interrupts • DMA (Direct memory Access)
A bus generally contains a set of control lines and a set of data lines. The control lines are used to signal requests and acknowledgments, and to indicate what type of information is on the data lines. The control lines are used to indicate what the bus contains and to implement the bus protocol. The data lines of the bus carry information between the source and the destination. This information may consist of data, complex commands, or addresses. Buses are traditionally classified as processor-memory di i ll l ifi d buses or I/O buses or special purposed buses (Graphics, etc. ). Processor memory buses are short, generally high speed, and matched to the memory system so as to maximize memoryprocessor bandwidth. I/O b buses, b contrast, can be lengthy, can have many by t t b l th h types of devices connected to them, and often have a wide range in the data bandwidth of the devices connected to them. I/O buses do not typically interface directly to the memory but use either a processor-memory or a backplane bus to connect to memory.
The major disadvantage of a bus is that it creates a communication bottleneck possibly limiting the maximum I/O bottleneck, throughput. When I/O must pass through a single bus, the bus bandwidth of that bus limits the maximum I/O throughput. Reason why b R h bus d i design is so difficult : i diffi lt - the maximum bus speed is largely limited by physical factors: the length of the bus and the number of devices. These physical limits prevent us from running the bus arbitrarily fast. - In addition, the need to support a range of devices with widely varying latencies and data transfer rates also makes bus design challenging. - it becomes difficult to run many parallel wires at high speed due to clock skew and reflection reflection.
The two basic schemes for communication on the bus are synchronous and asynchronous. If a bus is synchronous (e.g. Processor-memory), it includes a clock in the control lines and a fixed protocol for communicating that is relative to the clock. g This type of protocol can be implemented easily in a small finite state machine. Because the protocol is predetermined and involves little logic, the bus can run very fast and the interface logic will be small. Synchronous buses have two major disadvantages: - First, every device on the bus must run at the same clock rate. -...
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