This presents the use of a high language programming technique to implement image processing algorithms. FPGA is very instrumental in real time image processing because of the properties it holds. For example, FPGA has a structure that has ability to use temporal and special parallelism. This property is only unique to this kind of gates. Hardware constraints of the machine are another factor to consider because it affects the parallelism. Besides hardware constrains, processing mode is also another factor that affects parallelism. Computer engineers have sometimes been forced to change the settings of the algorithm sine the constraints were so illusive and in compatible. This paper is geared towards dealing with some sets of constraints for different types of image processing. INTRODUCTION
Computer scientists have always been challenged in their bid to implement real time image processing on serial processors. These difficulties have always been brought up by image properties such as large data sets, and complex operations that need to be performed on the image. In real time processing, 25 frames are witnessed every second. This alone contributes to redundancy and also adds to the slowing down of processing brought about by overheads of retrieval and storing of picture ingredients. In order to counteract the limitations that come with real time image processing, the use of field programmable gate arrays was discovered. FPGA have as a result brought about better revival in this industry (Hutchings, B. and Villasenor, J. pp. 67-84, Sep 1998). FPGA is an integrated circuit if numerous logic cells that are interconnected together for mutual coordination. Before the invention of FPGA, scientists always used fixed circuit of gates but this has numerous disadvantages in line with rigidity and expense. The coming of FPGA was welcomed with great gratitude and soon, these logic cells found application in numerous items. In the recent past, FPGA have gotten into the system of image processing applications. The FPGA consists of a series of logic cells that are brought together and connected using a switching network. The arrangement of logic gates can always be changed because of the programmable property of FPGA. This flexibility of arrangement of the logic gates means that the functions of the FPGA can also be changed from one mode to another (Downton, A. and Crookes, D. pp. 139-151, Jun, 1998). PARALLELISM IN IMAGE PROCESSING
Research in computer science field has so far yielded two types of parallelism in algorithms used in image processing. One of them is temporal parallelism, the other being spatial. The two types can be implemented in the FPGA through image partitioning so that the resulting sections can be spread and distributed to various pipelines. Both pipes are at times made to process data at the same time. Parallelism is always affected by the hardware that is used and the processing mode that is used. Constraints of the computer system are also a contributing factor. It is of great importance to look into some aspects of the hardware like priming, concurrency and pipelining. These properties have always brought great problems to computer scientists in the bid to implement algorithms touching on FPGA. Greater research to help counteract these challenges has resulted into more discoveries in high level language programming (Najjar, W. A., Draper, B. A. pp. 63-69, Aug, 2003). The use of high level programming languages has an advantage of lessening the whole process of algorithm writing. This works by hiding many details of low level caliber by allowing the compiler to do a lot of parallelism. This work is done automatically so that the programmer doesn’t need to face the harsh language head on. Loop unrolling is one of the optimization techniques that are use to extract parallelism. Temporary parallelism is also dealt with...