Hyper Threading Technology
HYPER-THREADING TECHNOLOGY
1. INTRODUCTION
This report describes the Hyper-Threading Technology architecture, and discusses the microarchitecture details of Intel's first implementation on the Intel Xeon processor family. For that reason, firstly, general processor microarchitecture and thread level parallelism will be explained. After that, hyper-threading technology architecture will be discussed in a detailed manner. Then, first implementation examples will be given. Also, some important components will be presented required for a hyper-threaded processor. After all, performace results of this new technology will conclude the report.
Hyper-Threading Technology brings the concept of simultaneous multi-threading to a general processor architecture. Hyper-Threading Technology makes a single physical processor appear as two logical processors; the physical execution resources are shared and the architecture state is duplicated for the two logical processors. From a software or architecture perspective, this means operating systems and user programs can schedule processes or threads to logical processors as they would on multiple physical processors. From a microarchitecture perspective, this means that instructions from both logical processors will persist and execute simultaneously on shared execution resources.
1. Processor Microarchitecture
Traditional approaches to processor design have focused on higher clock speeds, instruction-level parallelism (ILP), and caches. Techniques to achieve higher clock speeds involve pipelining the microarchitecture to finer granularities, also called super-pipelining. Higher clock frequencies can greatly improve performance by increasing the number of instructions that can be executed each second. Because there will be far more instructions in-flight in a super-pipelined microarchitecture, handling of events that disrupt the pipeline, e.g., cache misses, interrupts and branch mispredictions, can be costly.
ILP
1. INTRODUCTION
This report describes the Hyper-Threading Technology architecture, and discusses the microarchitecture details of Intel's first implementation on the Intel Xeon processor family. For that reason, firstly, general processor microarchitecture and thread level parallelism will be explained. After that, hyper-threading technology architecture will be discussed in a detailed manner. Then, first implementation examples will be given. Also, some important components will be presented required for a hyper-threaded processor. After all, performace results of this new technology will conclude the report.
Hyper-Threading Technology brings the concept of simultaneous multi-threading to a general processor architecture. Hyper-Threading Technology makes a single physical processor appear as two logical processors; the physical execution resources are shared and the architecture state is duplicated for the two logical processors. From a software or architecture perspective, this means operating systems and user programs can schedule processes or threads to logical processors as they would on multiple physical processors. From a microarchitecture perspective, this means that instructions from both logical processors will persist and execute simultaneously on shared execution resources.
1. Processor Microarchitecture
Traditional approaches to processor design have focused on higher clock speeds, instruction-level parallelism (ILP), and caches. Techniques to achieve higher clock speeds involve pipelining the microarchitecture to finer granularities, also called super-pipelining. Higher clock frequencies can greatly improve performance by increasing the number of instructions that can be executed each second. Because there will be far more instructions in-flight in a super-pipelined microarchitecture, handling of events that disrupt the pipeline, e.g., cache misses, interrupts and branch mispredictions, can be costly.
ILP
References: [1] http://arstechnica.com/articles/paedia/cpu/hyperthreading.ars [2] http://zone.ni.com/devzone/conceptd.nsf/webmain/opendocument [3] http://www.ni.com/labview/ [4] http://www.intel.com/technology/hyperthread/ [5] http://or1cedar.intel.com/media/training/intro_ht_dt_v1/tutorial/