Ht9170 Dtmf Decoder

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HT9170
DTMF Receiver
Features
·
·
·
·
·

Operating voltage: 2.5V~5.5V
Minimal external components
No external filter is required
Low standby current (on power down mode)
Excellent performance

·
·
·
·

Tristate data output for mC interface
3.58MHz crystal or ceramic resonator
1633Hz can be inhibited by the INH pin
HT9170B: 18-pin DIP package
HT9170D: 18-pin SOP package

General Description
DTMF tone pairs into a 4-bit code output.

The HT9170 series are Dual Tone Multi Frequency (DTMF) receivers integrated with digital decoder and bandsplit filter functions. The H T 9 1 7 0 B a nd H T 9 1 7 0 D t y p es s u p p l y
power-down mode and inhibit mode operations.
All types of the HT9170 series use digital counting techniques to detect and decode all the 16

Highly accurate switched capacitor filters are
employed to divide tone (DTMF) signals into
low and high group signals. A built-in dial tone
rejection circuit is provided to eliminate the
need for pre-filtering.

Selection Table
Function Operating
OSC
Tristate
Power 1633Hz
Voltage Frequency Data Output Down Inhibit
Part No.

DV DVB Package

HT9170B

2.5V~5.5V

3.58MHz

Ö

Ö

Ö

Ö

¾

18 DIP

HT9170D

2.5V~5.5V

3.58MHz

Ö

Ö

Ö

Ö

¾

18 SOP

1

December 20, 1999

HT9170
Block Diagram
PW DN

VREF

B ia s
C ir c u it

V re f
G e n e ra to r

R T /G T

EST

DV

DVB

X2
3 .5 8 M H z
C ry s ta l
O s c illa to r

X1

Low
VP

G ro u p
F ilte r

F re q u e n c y

P r e - F ilte r

OPA

VN

S te e r in g C o n tr o l C ir c u it

D e te c to r

H ig h G r o u p
F ilte r

GS

Code
D e te c to r

L a tc h
&
O u tp u t
B u ffe r

D0
D1
D2
D3

IN H

OE

Pin Assignment
VP
1

18

VDD

VP
1

18

VDD

VN
2

17

R T /G T

VN
2

17

R T /G T

GS
3

16

EST

GS
3

16

EST

VREF
4

15

DV

VREF
4

15

DV

IN H
5

14

D3

IN H
5

14

D3

PW DN
6

13

D2

PW DN
6

13

D2

X1
7

12

D1

X1
7

12

D1

X2
8

11

D0

X2
8

11

D0

VSS
9

10

OE

VSS
9

10

OE

HT9170B
1 8 D IP

HT9170D
18 SO P

2

December 20, 1999

HT9170
Pin Description
Pin Name I/O

Internal
Connection

Description

OPERATIONAL
Operational amplifier non-inverting input
AMPLIFIER

VP

I

VN

I

Operational amplifier inverting input

GS

O

Operational amplifier output terminal

VREF

O

X1

I

X2

O

PWDN

VREF

Reference voltage output, normally VDD/2

OSCILLATOR

The system oscillator consists of an inverter, a bias resistor and the necessary load capacitor on chip.
A standard 3.579545MHz crystal connected to X1 and X2 terminals implements the oscillator function.
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