High Level Design

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  • Topic: Electronic design automation, Logic synthesis, Design
  • Pages : 26 (8202 words )
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  • Published : April 5, 2013
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e‫אוניברסיטת בן-גוריון בנגב‬

Ben-Gurion University of the Negev
‫הפקולטה למדעי ההנדסה‬ ‫המחלקה להנדסת חשמל ומחשבים‬ Faculty of Engineering Science Dept. of Electrical and Computer Engineering

'‫פרויקט ההנדסי שנה ד‬
Fourth Year Engineering Project

‫דו"ח מכין‬ ( ‫תהליך תכנון מודל ב‬HLS ‫) בהשוואה לתהליך תכנון מסורתי ב‬HDL High Level Synthesis (HLS) compared to traditional HDL design flow approach Project number: Students (name & ID): Supervisors: s-2013-088 / p-2013-033 Lior Eckstein 036697076 Ron Sherf 037099207 Dr Shlomo Greenberg Mr. Idan Hahn Mr. Yaniv Fais :‫מספר הפרויקט‬ ‫סטודנטים‬ :).‫(שם ו ת.ז‬ :‫מנחים‬

Sponsors: Submitting date: 20.20.0220

:‫תומכים‬ :‫תאריך הגשה‬

Table of Contents
1.Abstract .......................................................................................................... 4 4 4 5 5 5 5 6 6 7 7 8 8 10 11 1.1Hebrew abstract ...................................................................................................... 1.2English abstract ....................................................................................................... 2.Preface ............................................................................................................ ....................................................................................... ....................................................................................... 3.The Project (Target) 4. Research Proposal

4.1.Project Name .......................................................................................................... 4.2.Introduction ............................................................................................................ .3.4Methodology .......................................................................................................... .3.3Outcomes and Benefits of This Project ................................................................. 4.5.Evaluation and Measurement ................................................................................. .5Literature Exploration ................................................................................. 5.1.Basic Terms ........................................................................................................... 5.2.General background ............................................................................................... 5.3.Pros and cons of the Main approaches to hardware description and synthesis ..... 5.3.1.Register transfer level synthesis By Hardware description language 5.3.2.High-level synthesis 5.4.1.Key concepts 5.4.3.Specifying Micro-architecture 5.4.4.Allocation 5.4.5.Scheduling 5.4.6.Binding 5.4.7.Generation

………...11 15

……………………………………………12 ……………………………………………15 ……………………….………16 ……………………………………………18 ……………………………………………21 ……………………………………………22 ……………………………………………23 …………....................................................23 23 24 27 28 28 28 28 28 28 29 29

5.4.HLS Design Flow .................................................................................................. 5.4.2.Implement the specification at c\c++\SysemC

5.5.RTL Architecture ................................................................................................... 5.6.Synthesis output model flavors and checking the model view .............................. 6.Planning Proposal .......................................................................................... 6.1.Project constraints .................................................................................................. 6.2.Project assumptions ............................................................................................... 6.3.Initial defined risks ................................................................................................ 6.4.Product Essence ..................................................................................................... 6.5.Project scope...
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