Gate: X86 and Accumulator

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  • Topic: X86, Status register, Instruction set
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  • Published : April 4, 2013
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BAPATLA ENGINEERING COLLEGE :: BAPATLA
DEPARTMENT OF ECE

GATE – 2010

MICROPROCESSORS AND INTERFACING

Faculty: Sri A.M.V.N.Maruthi

1) The width of address bus and data bus in 8085 are respectively…

a) 16,8 b)8,16

c) 8,8 d) 16,16

2) The number of status flags in 8085 are

a) 5 b) 6

c)9 d)8

3) The status that cannot be operated by direct instructions is

a) Cy b) Z

c) P d) AC

4) The number of software interrupts in 8085 is…

a) 5 b) 8

c) 9 d) 10

5) Identify the non maskabe interrupt in the following

a) RST4.5 b) RST5.5

c) RST6.5 d) RST 7.5

6) If the contents of SP are 1000H, the content of B and C registers after PUSH B instruction

are...

a)0FFFH, OFFEH b) 0FFE H ,0FFF H

c) 1000 H,0FFF H d) 1000 H, 1001H

7) In an 8085 system, let SP=20000 H. Then after execution of POP H instruction will transfer the memory contents as…

a) 2001H and 2002H to H and L register b) 2001H and 2000H in to H and L registers

c) 2000H and 1FFFH to H and L registers d) 2000H and 1999H to H and L registers

8) In response to RST 7.5 interrupt, the execution of control transfers to memory location...

a) 0000H b) 002CH

c)0034H d) 003CH

9) Let contents of accumulator and B are 00000100 and 01000000 respectively. After

execution of SUB B instruction, accumulator contents are….

a) 00000100 b) 01000000

c) 11000100 d) 010001000

10) Let the contents of C register be 00000000. The contents of C register after execution of

DCR C is..

a) 00000000 b) 11111111

c) 00000001 d) none of above

11) In an 8085 based system, the maximum number of input output devices can be connected

using I/0 mapped I/O method is

a) 64 b) 512

c) 256 d) 65536

12) Which of following is both level and edge sensitive?

a) RST 7.5 b) RST 5.5

c) TRAP d) INTR

13) After the execution of CMA instruction, the status of Z and Cy flags are respectively..

a) set, reset b) set, unchanged

c) reset, set d)reset, unchanged

14) The 8085 will enter in to INA cycle after the execution of…

a) any interrupt b)TRAP only

c) INTR only d) RST 7.5,6.5,5.5 only

15) The interrupt vector address for TRAP is

a)0000H b) 0024H

c)0018H d) 002CH

16) To reset carry without affecting accumulator contents, we have to use

a) SUB A b) XRA A

c)ORA A d)CMC

17) The status of S0 and S1 pins for memory read is.

a) 00 b)01

c)10 d)11

18) In order to complement the lower order nibble of the accumulator, we can use …

a) ANI 0FH b) XRI 0FH

c) ORI 0FH d)CMA

19) Which of the following instruction will never affect the zero flag..

a)DCR reg b) ORA reg

c)DCX rp d) XRA reg

20) The interface peripheral used with key board is

a)8251 b) 8279

c)8259 d)8253

21) The execution of RST n instruction causes the stack pointer to ..

a) Incremented by two b) decremented by two

c)remain unaffected d) none of the above

22) To save accumulator value on to the stack, which of the following instructions may be

used..

a)PUSH PSW b) PUSH A

c) PUSH SP d) POP PSW

23) A single instruction to clear the lower 4 bits of accumulator in 8085 alp is..

a) XRI 0FH...
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