Topics: Semiconductor device fabrication, Die, Semiconductor Pages: 42 (8048 words) Published: March 8, 2013


1. Background of the Study
The Wafer Level Chip Scale Package (WLCSP) in the semiconductor product is the only true chip size package, because for the WLCSP the die itself is the package. The Silicon Wafer Dicing Saw in the semiconductor industry is one of the most critical processes for Wafer Level Chip Scale Package. The Analog Devices Inc. Gen. Trias (ADGT) has recently qualified its manufacturing facility for WLCSP products, and for the last six months of the operation, the most frequently encountered problem for WLCSP- Wafer Dicing Saw process is the wafer die edge chipping for both top side and backside of the silicon chip. The product with edge chipping reject affects the electrical performance of the IC and eventually fails on the field of its application. In this case, the performance of the company is greatly affected by the higher rate of rejected products and eventually reduced its profits including the possible lost of its potential customers. The researcher being the process owner for the WLCSP wafer dicing saw process, was given a task to make an experiment for the solution of the problem, to eliminate edge chipping problem to increase the manufacturing yield performance and eventually qualifies the process of back coated wafer material for WLCSP product, as a solution to wafer die edge chipping problem that causes the electrical failure of the IC product. The plastic back coated wafer is being evaluated including the appropriate diamond dicing blade by the researcher as a solution to the problem. The back coating solution for silicon wafers is intended to protect the die backside from the die chippings and avoid the electrical failure of the IC. The silicon wafer fabrication division endorsed the three sample wafers to the researcher to be used on the experiment and qualification. The three samples of silicon wafer with semiconductor back coated tape would be used to characterize the WLCSP process for the back coated wafers. The two wafers for the checkout – characterization activity, and the remaining wafer to be shipped will be used as customer samples.

1.2 Objectives of Study
To accomplish this project study, the following are the objectives: 1. To design a modified dicing saw process for Wafer Level Chip Scale Package (WLCSP). 2. To evaluate the efficiency of the back coated silicon Wafer Level Chip Scale Package (WLCSP) and its appropriate diamond dicing blade for ADGT thru Design of Experiment. 3. To eliminate product electrical failure due to edge chipping problem and increase production yield performance.

1.3 Conceptual Framework
The Backside chipping or the die edge chipping problem is one of the well known problems in the field of Semiconductor manufacturing industry. This is due to different factors affecting the process during the wafer cutting. However, many strategies and studies are made by different semiconductor companies to correct the problem of their own process. But in the case of ADGT, the newly qualified WLCSP wafer product is much sensitive and more critical in the dicing saw process because of its unique material composition of silicon glass and the redistribution layers used in the IC wafer fabrication on Flip chip or bumped wafers which is prone to edge chipping problem. The ADGT wafer saw manufacturing frequently encounters a low yielding lot on WLCSP product due to edge chipping problem on both backside and topside of the wafer. With the qualification of the new technology design of back coated wafers and the appropriate diamond dicing blade for wafer saw process, the edge chipping problem can be eliminated. The Figure 1 below shows Conceptual Paradigm devised by the researcher. The Input:

➢ To study the diamond dicing blade and the plastic back coated wafers to eliminate the problem on edge chippings at wafer saw process. ➢ Gather...
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