# Electrical Distribution Feeder Analysis

**Topics:**Voltage, Electronics terms, Voltage drop

**Pages:**5 (1240 words)

**Published:**November 29, 2010

Distribution Feeder Analysis

11/29/2010

Kris Bartell

Matt Drzewiecki

Evan Zaborski

1.0Abstract

This project offered the opportunity to simulate the voltage profile of an IEEE sample distribution feeder. Through an iterative process, this can be accomplished using a series of calculations. To achieve this goal, the simulation package Matlab was used as the driving force behind the programming and calculating.

Discussion

2.1 Individual Segment Modeling

To simulate the feeder, the first thing needed is a model of each line segment. To construct this model, code can be written that computes the distances between conductors by using the configurations and conductor values given for each line segment. These results provide the information needed to create the primitive impedance matrix, Zprim. Using the matrix operation known as Kron reduction, shown in Equation (1) below, these primitive matrices can be converted into Zabc impedance matrices. Z=A-BC^(-1) D (1)

Each matrix can then be multiplied by its respective segment length to convert to actual ohmic values of line resistance. These matrices represent the main part of the line model. 2.2 Load Modeling

Each load connected to the feeder can now be modeled. To accurately simulate the voltage profile, three types of loads will be modeled. These include a constant current load, a constant impedance load, and a load with constant real and reactive power. To simplify needed calculations, each delta-connected load shall be converted to a wye-connected load using Equation (2). Z_Υ=Z_Δ/3 (2)

The current required for each load can now be calculated based on the nominal line voltage. 2.3 Iterative Process

Using these currents the voltage drop can be computed for each line segment. Now the second part of the iteration can begin, calculating the voltages at all the nodes. Using the voltage drops the new node voltages can be computed. After the node voltages have been calculated the new currents required from each load are computed based on the new voltage. This iterative process is repeated until the error is smaller than the desired error specification, which is usually around 1*10-4 p.u. When the desired error specification is met, the final node voltages are calculated. Using the voltages and line impedances, the power flow and power losses can be calculated. The voltage profile of the feeder can also be calculated. After finding the voltage profile of the feeder, the setting of the voltage regulator can be determined.

Results and Analysis

3.1 Case 1: PF Correction Enabled, Sectionalizer Closed

There are four main cases that were considered in the modeling of the 13 bus test system. The first case that was considered was with the sectionalizer between nodes 671 and 692 closed, and all of the power factor correction capacitors connected. The voltage profile can be seen in Figure 3.1.1. Figure 3.1.1: Case 1 Voltage Profile by Node

As can be seen, there is a large difference between the ‘B’ phase and the other phases. This is due to the configuration of the loads. The ‘B’ phase has the smallest connected load. In this case, minimal single and 2 phase segments are present on the ‘B’ phase conductor, so the voltage does not fluctuate during these segments. Upon examination of Figure 3.1.1, it can be seen that only the ‘B’ phase remains in the voltage tolerance. Though it may be possible to regulate all 3 phases to meet the minimum tolerance, it was outside of the scope of this simulation and was therefore not explored. 3.2. Case 2: PF Correction Disabled, Sectionalizer Closed

In case 2, the sectionalizer between nodes 671 and 692 was closed and all of the power factor correction capacitors are disconnected. As shown in Figure 3.2.1, all of the voltages are lower magnitudes than case 1, which is expected due to the increased current. The voltage profile ‘B’ phase is marginally acceptable without voltage regulation....

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