The objective of this assignment is to design and construct a car park digital controller circuit for 99 car parking slots using sequential and combinational logic circuits. The circuits will receive the digital signals from two sensors located at the ENTRANCE and EXIT of the car park to display the number of empty slots and to display the word FULL in case of no more empty slots.
We need to monitor the number of empty slots in the parking areas by setting up a sensor EN allocated in the ENTRANCE whereas the output of this sensor is HIGH (1) when there is a car entering the parking area. On the other hand, EX is allocated in the EXIT; the output of this sensor is HIGH (1) when there is a car leaving the parking areas. Hence, both of the sensors are connected to a sequential digital circuit for which we call it an up-down counter for which the circuit is used to count the number of cars entering and exiting the parking areas; the output of this circuit is connected to the 7-segments decoder to convert each BCD code to ten possible number from 0 to 9 in order display the number of empty slots available and to display the word FULL when there are no empty parking slots available as shown below:
The 7-segments display board
Figure 1: Processes involved in displaying number of empty slots available and ‘FULL’ Design Procedure:
1. Synchronous BCD Up -down Counter
* One BCD up-down counter only responsible to count from 0 to 9. In order to count from 00 to 99, we then need to cascade two BCD up-down counters together. * The counter can enable either the top counting mode or the down counting mode between the numbers lies between two limits of 00 to 99. * The minimum count that this circuit can count down to is 00; the maximum count is 99. * The output of the counter is display in binary code and in order to show that we then need to add on a probe in each of the output for QA, QB, QC and QD. * The output of two BCD up-down counter after cascaded should be displayed using the two 7-segments display where one is used for the Least Significant Bit (LSB) and another for the Most Significant Bit (MSB). The reason for this is because when both counters counts 0, the world FULL will be display through another four 7-segments displays
We are using switches to provide inputs to the digital controller circuit instead of using the sensors. One switch is used to count up (when the car is leaving the parking slots) and another one is used to count down (when the car is entering the parking slots). J-K flip-flops are mainly used to design the up-down counter that we are currently using to display the numbers of empty parking slots available for the drivers. The operation of the J-K flip flop can be summarized by the following truth table:
J| K| | Qn+1| | Action in the next clock pulse|
0| 0| | Qn| | No change, Qn+1=Qn|
0| 1| | 0| | Reset, Qn+1=0|
1| 0| | 1| | Set, Qn+1=1|
1| 1| | Qn| | Toggle, Qn+1=Qn|
Table 1: Truth Table for J-K Flip-flops
In a synchronous counter, all the flip-flops are triggered simultaneously by the clock pulse. In my design, the clock pulse from all flips-flops is generated synchronously by connecting both switches together using NOR gates as shown in Circuit 1. The J and K inputs are used to control when each flip-flop is to toggle or remain unaffected by a clock pulse. Now, let us assume that Y = 0 when we are counting down; Y = 1 when we are counting up for JKD, JKC, JKB and JKA.
Figure 2: State Diagram for counting up
Present State| | Next State(UP)| | |
QA| QB| QC| QD| | QA| QB| QC| QD| | JKA| JKB| JKC| JKD| 0| 0| 0| 0| | 0| 0| 0| 1| | 0| 0| 0| 1|
0| 0| 0| 1| | 0| 0| 1| 0...