EE 316: Advanced VLSI Devices Lecture 4 – Device Scaling and Short Channel Effects H.-S. H S Philip Wong Professor of Electrical Engineering Stanford University, Stanford, California, U.S.A. hspwong@stanford.edu hspwong@stanford edu http://www.stanford.edu/~hspwong Center for Integrated Systems EE 316

Department of Electrical Engineering

Stanford University

Questions? Q ti ?

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H.-S. Philip Wong

EE 316

Department of Electrical Engineering

Stanford University

Topics To Be Covered (1 of 2)

Overview of the semiconductor industry

Done Done

MOSFET – MOS capacitor, MOSFET long channel behavior p , g Short-channel MOSFET Device modeling

Si MOSFET device scaling, non-scaling factors, reading the ITRS

– TCAD tools, fundamentals of numerical device simulation, interpretation of device simulation results and tricks of the trade – TA sessions for Sentaurus modeling tool prior to lecture MOSFET electrostatics – Channel length, scale length theory, minimum channel length – PDSOI, FDSOI, double-gate, FinFET, multi-gate FET – Threshold voltage, quantum effects – Non-uniform channel doping, halo, super-halo MOSFET electrodynamics – Carrier mobility, velocity saturation, scattering theory, ballistic transport – Strain effects 4-3 H.-S. Philip Wong EE 316 Department of Electrical Engineering

Stanford University

MOSFET Scaling g

Device scaling: Simplified design goals/guidelines for shrinking device dimensions Goals: Achieve density and performance gains, and power reduction in VLSI. Issues: Short-channel effect, Power density, Switching delay, Reliability.

Constant-field scaling: Scale the device voltages and the device dimensions (both horizontal and vertical) by the same factor ( 1) factor, 1), such that the electric field remains unchanged. 4-4 H.-S. Philip Wong EE 316 Department of Electrical Engineering

Stanford University

Rules of Constant Field Scaling g

MOSFET Device and Circuit Parameters Device dimensions (tox, L, W, xj) ( , , Doping concentration (Na, Nd) Voltage (V) Derived scaling behavior of device parameters Electric field (E) Carrier velocity (v) Depletion layer width (Wd) Capacitance (C = A/t) Inversion layer charge density (Qi) Current, drift (I) Channel resistance (Rch) Derived scaling behavior of circuit parameters Circuit delay time ( CV/I) Power dissipation per circuit (P VI) Power-delay product per circuit (P) Circuit density (1/A) Power density ( y (P/A) ) Multiplicative Factor ( > 1) 1/

Scaling assumptions S li ti

1/ 1 1 1/ 1/ 1 1/ 1 1/ 1/2 1/3

2

1

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H.-S. Philip Wong

EE 316

Department of Electrical Engineering

Stanford University

Device Scaling History

IEEE Solid State Circuits Society Newsletter (Jan 2007): – http://www.ieee.org/po rtal/cms_docs_societie rtal/cms docs societie s/sscs/PrintEditions/20 0701.pdf

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H.-S. Philip Wong

EE 316

Department of Electrical Engineering

Stanford University

Device Scaling Reference

4-7

H.-S. Philip Wong

EE 316

Department of Electrical Engineering

Stanford University

Questions? Q ti ?

4-8

H.-S. Philip Wong

EE 316

Department of Electrical Engineering

Stanford University

Generalized Scaling g

Allow electric field to scale up by (E E), while the device dimensions scale down by (x, y, z x/, y/, z/), i.e. i e voltage scales by / (V ( / )V) (/)V). More flexible than constant-field scaling, but has reliability and power concerns concerns. 3D Poisson’s equation:

1 1

2 2 2 q 2 2 p ( x, y , z ) n ( x, y , z ) N d ( x, y , z ) N a ( x, y , z ) x 2 y z Si

To keep Poisson’s equation invariant (within the depletion region) under the transformation, (x,y,z) (x,y,z)/ and (/ ) : 2 ( / ) 2 ( / ) 2 ( / ) q [ p ( x, y , z ) n( x, y , z ) N d ( x, y , z ) N a ( x, y , z )] (...